/** * Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the * transmitter, and the receiver. * * Steps to reset * - Stops transmit and receive channels * - Stops DMA * - Configure transmit and receive buffer size to default * - Clear transmit and receive status register and counters * - Clear all interrupt sources * - Clear phy (if there is any previously detected) address * - Clear MAC addresses (1-4) as well as Type IDs and hash value * * All options are placed in their default state. Any frames in the * descriptor lists will remain in the lists. The side effect of doing * this is that after a reset and following a restart of the device, frames * were in the list before the reset may be transmitted or received. * * The upper layer software is responsible for re-configuring (if necessary) * and restarting the MAC after the reset. Note also that driver statistics * are not cleared on reset. It is up to the upper layer software to clear the * statistics if needed. * * When a reset is required, the driver notifies the upper layer software of * this need through the ErrorHandler callback and specific status codes. * The upper layer software is responsible for calling this Reset function * and then re-configuring the device. * * @param InstancePtr is a pointer to the instance to be worked on. * ******************************************************************************/ void XEmacPs_Reset(XEmacPs *InstancePtr) { u32 Reg; u8 i; char EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; Xil_AssertVoid(InstancePtr != NULL); Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* Stop the device and reset hardware */ XEmacPs_Stop(InstancePtr); InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS; /* Setup hardware with default values */ XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, (XEMACPS_NWCTRL_STATCLR_MASK | XEMACPS_NWCTRL_MDEN_MASK) & ~XEMACPS_NWCTRL_LOOPEN_MASK); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET, XEMACPS_NWCFG_100_MASK | XEMACPS_NWCFG_FDEN_MASK | XEMACPS_NWCFG_UCASTHASHEN_MASK); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, ((((XEMACPS_RX_BUF_SIZE / XEMACPS_RX_BUF_UNIT) + ((XEMACPS_RX_BUF_SIZE % XEMACPS_RX_BUF_UNIT) ? 1 : 0)) << XEMACPS_DMACR_RXBUF_SHIFT) & XEMACPS_DMACR_RXBUF_MASK) | XEMACPS_DMACR_RXSIZE_MASK | XEMACPS_DMACR_TXSIZE_MASK); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_TXSR_OFFSET, 0x0); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_RXQBASE_OFFSET, 0x0); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_TXQBASE_OFFSET, 0x0); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_RXSR_OFFSET, 0x0); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, XEMACPS_IXR_ALL_MASK); Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, Reg); XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_PHYMNTNC_OFFSET, 0x0); XEmacPs_ClearHash(InstancePtr); for (i = 1; i < 5; i++) { XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i); XEmacPs_SetTypeIdCheck(InstancePtr, 0x0, i); } /* clear all counters */ for (i = 0; i < (XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4; i++) { XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_OCTTXL_OFFSET + i * 4); } /* Disable the receiver */ Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCTRL_OFFSET); Reg &= ~XEMACPS_NWCTRL_RXEN_MASK; XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCTRL_OFFSET, Reg); /* Sync default options with hardware but leave receiver and * transmitter disabled. They get enabled with XEmacPs_Start() if * XEMACPS_TRANSMITTER_ENABLE_OPTION and * XEMACPS_RECEIVER_ENABLE_OPTION are set. */ XEmacPs_SetOptions(InstancePtr, InstancePtr->Options & ~(XEMACPS_TRANSMITTER_ENABLE_OPTION | XEMACPS_RECEIVER_ENABLE_OPTION)); XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options); }
/** * * This function demonstrates the usage of the EMACPS by sending and * receiving a single frame in DMA interrupt mode. * The source packet will be described by two descriptors. It will be * received into a buffer described by a single descriptor. * * @param EmacPsInstancePtr is a pointer to the instance of the EmacPs * driver. * * @return XST_SUCCESS to indicate success, otherwise XST_FAILURE. * * @note None. * *****************************************************************************/ int EmacPsDmaSingleFrameIntrExample(XEmacPs *EmacPsInstancePtr) { int Status; u32 PayloadSize = 1000; u32 NumRxBuf = 0; XEmacPs_Bd *Bd1Ptr; XEmacPs_Bd *Bd2Ptr; XEmacPs_Bd *BdRxPtr; /* * Clear variables shared with callbacks */ FramesRx = 0; FramesTx = 0; DeviceErrors = 0; /* * Calculate the frame length (not including FCS) */ TxFrameLength = XEMACPS_HDR_SIZE + PayloadSize; /* * Setup packet to be transmitted */ EmacPsUtilFrameHdrFormatMAC(&TxFrame, EmacPsMAC); EmacPsUtilFrameHdrFormatType(&TxFrame, PayloadSize); EmacPsUtilFrameSetPayloadData(&TxFrame, PayloadSize); Xil_DCacheFlushRange((u32)&TxFrame, TxFrameLength); /* * Clear out receive packet memory area */ EmacPsUtilFrameMemClear(&RxFrame); Xil_DCacheFlushRange((u32)&RxFrame, TxFrameLength); /* * Allocate RxBDs since we do not know how many BDs will be used * in advance, use RXBD_CNT here. */ Status = XEmacPs_BdRingAlloc(& (XEmacPs_GetRxRing(EmacPsInstancePtr)), 1, &BdRxPtr); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error allocating RxBD"); return XST_FAILURE; } /* * Setup the BD. The XEmacPs_BdRingClone() call will mark the * "wrap" field for last RxBD. Setup buffer address to associated * BD. */ XEmacPs_BdSetAddressRx(BdRxPtr, &RxFrame); /* * Enqueue to HW */ Status = XEmacPs_BdRingToHw(&(XEmacPs_GetRxRing(EmacPsInstancePtr)), 1, BdRxPtr); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error committing RxBD to HW"); return XST_FAILURE; } /* * Allocate, setup, and enqueue 2 TxBDs. The first BD will * describe the first 32 bytes of TxFrame and the rest of BDs * will describe the rest of the frame. * * The function below will allocate 2 adjacent BDs with Bd1Ptr * being set as the lead BD. */ Status = XEmacPs_BdRingAlloc(&(XEmacPs_GetTxRing(EmacPsInstancePtr)), 2, &Bd1Ptr); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error allocating TxBD"); return XST_FAILURE; } /* * Setup first TxBD */ XEmacPs_BdSetAddressTx(Bd1Ptr, &TxFrame); XEmacPs_BdSetLength(Bd1Ptr, FIRST_FRAGMENT_SIZE); XEmacPs_BdClearTxUsed(Bd1Ptr); XEmacPs_BdClearLast(Bd1Ptr); /* * Setup second TxBD */ Bd2Ptr = XEmacPs_BdRingNext(&(XEmacPs_GetTxRing(EmacPsInstancePtr)), Bd1Ptr); XEmacPs_BdSetAddressTx(Bd2Ptr, (u32) (&TxFrame) + FIRST_FRAGMENT_SIZE); XEmacPs_BdSetLength(Bd2Ptr, TxFrameLength - FIRST_FRAGMENT_SIZE); XEmacPs_BdClearTxUsed(Bd2Ptr); XEmacPs_BdSetLast(Bd2Ptr); /* * Enqueue to HW */ Status = XEmacPs_BdRingToHw(&(XEmacPs_GetTxRing(EmacPsInstancePtr)), 2, Bd1Ptr); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error committing TxBD to HW"); return XST_FAILURE; } /* * Start the device */ XEmacPs_Start(EmacPsInstancePtr); /* Start transmit */ XEmacPs_Transmit(EmacPsInstancePtr); /* * Wait for transmission to complete */ while (!FramesTx); /* * Now that the frame has been sent, post process our TxBDs. * Since we have only submitted 2 to hardware, then there should * be only 2 ready for post processing. */ if (XEmacPs_BdRingFromHwTx(&(XEmacPs_GetTxRing(EmacPsInstancePtr)), 2, &Bd1Ptr) == 0) { EmacPsUtilErrorTrap ("TxBDs were not ready for post processing"); return XST_FAILURE; } /* * Examine the TxBDs. * * There isn't much to do. The only thing to check would be DMA * exception bits. But this would also be caught in the error * handler. So we just return these BDs to the free list. */ Status = XEmacPs_BdRingFree(&(XEmacPs_GetTxRing(EmacPsInstancePtr)), 2, Bd1Ptr); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error freeing up TxBDs"); return XST_FAILURE; } /* * Wait for Rx indication */ while (!FramesRx); /* * Now that the frame has been received, post process our RxBD. * Since we have submitted to hardware, then there should be only 1 * ready for post processing. */ NumRxBuf = XEmacPs_BdRingFromHwRx(&(XEmacPs_GetRxRing (EmacPsInstancePtr)), 1, &BdRxPtr); if (0 == NumRxBuf) { EmacPsUtilErrorTrap("RxBD was not ready for post processing"); return XST_FAILURE; } /* * There is no device status to check. If there was a DMA error, * it should have been reported to the error handler. Check the * receive lengthi against the transmitted length, then verify * the data. */ if ((XEmacPs_BdGetLength(BdRxPtr)) != TxFrameLength) { EmacPsUtilErrorTrap("Length mismatch"); return XST_FAILURE; } if (EmacPsUtilFrameVerify(&TxFrame, &RxFrame) != 0) { EmacPsUtilErrorTrap("Data mismatch"); return XST_FAILURE; } /* * Return the RxBD back to the channel for later allocation. Free * the exact number we just post processed. */ Status = XEmacPs_BdRingFree(&(XEmacPs_GetRxRing(EmacPsInstancePtr)), NumRxBuf, BdRxPtr); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error freeing up RxBDs"); return XST_FAILURE; } /* * Finished this example. If everything worked correctly, all TxBDs * and RxBDs should be free for allocation. Stop the device. */ XEmacPs_Stop(EmacPsInstancePtr); return XST_SUCCESS; }
/** * This function resets the device but preserves the options set by the user. * * The descriptor list could be reinitialized with the same calls to * XEmacPs_BdRingClone() as used in main(). Doing this is a matter of * preference. * In many cases, an OS may have resources tied up in the descriptors. * Reinitializing in this case may bad for the OS since its resources may be * permamently lost. * * @param EmacPsInstancePtr is a pointer to the instance of the EmacPs * driver. * * @return XST_SUCCESS if successful, else XST_FAILURE. * * @note None. * *****************************************************************************/ static int EmacPsResetDevice(XEmacPs * EmacPsInstancePtr) { int Status = 0; u8 MacSave[6]; u32 Options; XEmacPs_Bd BdTemplate; /* * Stop device */ XEmacPs_Stop(EmacPsInstancePtr); /* * Save the device state */ XEmacPs_GetMacAddress(EmacPsInstancePtr, &MacSave, 1); Options = XEmacPs_GetOptions(EmacPsInstancePtr); /* * Stop and reset the device */ XEmacPs_Reset(EmacPsInstancePtr); /* * Restore the state */ XEmacPs_SetMacAddress(EmacPsInstancePtr, &MacSave, 1); Status |= XEmacPs_SetOptions(EmacPsInstancePtr, Options); Status |= XEmacPs_ClearOptions(EmacPsInstancePtr, ~Options); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error restoring state after reset"); return XST_FAILURE; } /* * Setup callbacks */ Status = XEmacPs_SetHandler(EmacPsInstancePtr, XEMACPS_HANDLER_DMASEND, (void *) XEmacPsSendHandler, EmacPsInstancePtr); Status |= XEmacPs_SetHandler(EmacPsInstancePtr, XEMACPS_HANDLER_DMARECV, (void *) XEmacPsRecvHandler, EmacPsInstancePtr); Status |= XEmacPs_SetHandler(EmacPsInstancePtr, XEMACPS_HANDLER_ERROR, (void *) XEmacPsErrorHandler, EmacPsInstancePtr); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error assigning handlers"); return XST_FAILURE; } /* * Setup RxBD space. * * We have already defined a properly aligned area of memory to store * RxBDs at the beginning of this source code file so just pass its * address into the function. No MMU is being used so the physical and * virtual addresses are the same. * * Setup a BD template for the Rx channel. This template will be copied * to every RxBD. We will not have to explicitly set these again. */ XEmacPs_BdClear(&BdTemplate); /* * Create the RxBD ring */ Status = XEmacPs_BdRingCreate(&(XEmacPs_GetRxRing (EmacPsInstancePtr)), RX_BD_LIST_START_ADDRESS, RX_BD_LIST_START_ADDRESS, XEMACPS_BD_ALIGNMENT, RXBD_CNT); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap ("Error setting up RxBD space, BdRingCreate"); return XST_FAILURE; } Status = XEmacPs_BdRingClone(& (XEmacPs_GetRxRing(EmacPsInstancePtr)), &BdTemplate, XEMACPS_RECV); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap ("Error setting up RxBD space, BdRingClone"); return XST_FAILURE; } /* * Setup TxBD space. * * Like RxBD space, we have already defined a properly aligned area of * memory to use. * * Also like the RxBD space, we create a template. Notice we don't set * the "last" attribute. The examples will be overriding this * attribute so it does no good to set it up here. */ XEmacPs_BdClear(&BdTemplate); XEmacPs_BdSetStatus(&BdTemplate, XEMACPS_TXBUF_USED_MASK); /* * Create the TxBD ring */ Status = XEmacPs_BdRingCreate(&(XEmacPs_GetTxRing (EmacPsInstancePtr)), TX_BD_LIST_START_ADDRESS, TX_BD_LIST_START_ADDRESS, XEMACPS_BD_ALIGNMENT, TXBD_CNT); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap ("Error setting up TxBD space, BdRingCreate"); return XST_FAILURE; } Status = XEmacPs_BdRingClone(& (XEmacPs_GetTxRing(EmacPsInstancePtr)), &BdTemplate, XEMACPS_SEND); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap ("Error setting up TxBD space, BdRingClone"); return XST_FAILURE; } /* * Restart the device */ XEmacPs_Start(EmacPsInstancePtr); return XST_SUCCESS; }
/** * * This function demonstrates the usage of the EmacPs driver by sending by * sending and receiving frames in interrupt driven DMA mode. * * * @param IntcInstancePtr is a pointer to the instance of the Intc driver. * @param EmacPsInstancePtr is a pointer to the instance of the EmacPs * driver. * @param EmacPsDeviceId is Device ID of the EmacPs Device , typically * XPAR_<EMACPS_instance>_DEVICE_ID value from xparameters.h. * @param EmacPsIntrId is the Interrupt ID and is typically * XPAR_<EMACPS_instance>_INTR value from xparameters.h. * * @return XST_SUCCESS to indicate success, otherwise XST_FAILURE. * * @note None. * *****************************************************************************/ int EmacPsDmaIntrExample(XScuGic * IntcInstancePtr, XEmacPs * EmacPsInstancePtr, u16 EmacPsDeviceId, u16 EmacPsIntrId) { int Status; XEmacPs_Config *Config; XEmacPs_Bd BdTemplate; #ifndef PEEP u32 SlcrTxClkCntrl; #endif /*************************************/ /* Setup device for first-time usage */ /*************************************/ /* SLCR unlock */ *(volatile unsigned int *)(SLCR_UNLOCK_ADDR) = SLCR_UNLOCK_KEY_VALUE; #ifdef PEEP *(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SLCR_GEM_1G_CLK_CTRL_VALUE; *(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR) = SLCR_GEM_1G_CLK_CTRL_VALUE; #else if (EmacPsIntrId == XPS_GEM0_INT_ID) { #ifdef XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 /* GEM0 1G clock configuration*/ SlcrTxClkCntrl = *(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR); SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK; SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 << 20); SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 << 8); *(volatile unsigned int *)(SLCR_GEM0_CLK_CTRL_ADDR) = SlcrTxClkCntrl; #endif } else if (EmacPsIntrId == XPS_GEM1_INT_ID) { #ifdef XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 /* GEM1 1G clock configuration*/ SlcrTxClkCntrl = *(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR); SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK; SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 << 20); SlcrTxClkCntrl |= (XPAR_PS7_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 << 8); *(volatile unsigned int *)(SLCR_GEM1_CLK_CTRL_ADDR) = SlcrTxClkCntrl; #endif } #endif /* SLCR lock */ *(unsigned int *)(SLCR_LOCK_ADDR) = SLCR_LOCK_KEY_VALUE; sleep(1); /* * Initialize instance. Should be configured for DMA * This example calls _CfgInitialize instead of _Initialize due to * retiring _Initialize. So in _CfgInitialize we use * XPAR_(IP)_BASEADDRESS to make sure it is not virtual address. */ Config = XEmacPs_LookupConfig(EmacPsDeviceId); Status = XEmacPs_CfgInitialize(EmacPsInstancePtr, Config, Config->BaseAddress); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error in initialize"); return XST_FAILURE; } /* * Set the MAC address */ Status = XEmacPs_SetMacAddress(EmacPsInstancePtr, EmacPsMAC, 1); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error setting MAC address"); return XST_FAILURE; } /* * Setup callbacks */ Status = XEmacPs_SetHandler(EmacPsInstancePtr, XEMACPS_HANDLER_DMASEND, (void *) XEmacPsSendHandler, EmacPsInstancePtr); Status |= XEmacPs_SetHandler(EmacPsInstancePtr, XEMACPS_HANDLER_DMARECV, (void *) XEmacPsRecvHandler, EmacPsInstancePtr); Status |= XEmacPs_SetHandler(EmacPsInstancePtr, XEMACPS_HANDLER_ERROR, (void *) XEmacPsErrorHandler, EmacPsInstancePtr); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap("Error assigning handlers"); return XST_FAILURE; } /* * The BDs need to be allocated in uncached memory. Hence the 1 MB * address range that starts at address 0xFF00000 is made uncached. */ Xil_SetTlbAttributes(0x0FF00000, 0xc02); /* * Setup RxBD space. * * We have already defined a properly aligned area of memory to store * RxBDs at the beginning of this source code file so just pass its * address into the function. No MMU is being used so the physical * and virtual addresses are the same. * * Setup a BD template for the Rx channel. This template will be * copied to every RxBD. We will not have to explicitly set these * again. */ XEmacPs_BdClear(&BdTemplate); /* * Create the RxBD ring */ Status = XEmacPs_BdRingCreate(&(XEmacPs_GetRxRing (EmacPsInstancePtr)), RX_BD_LIST_START_ADDRESS, RX_BD_LIST_START_ADDRESS, XEMACPS_BD_ALIGNMENT, RXBD_CNT); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap ("Error setting up RxBD space, BdRingCreate"); return XST_FAILURE; } Status = XEmacPs_BdRingClone(&(XEmacPs_GetRxRing(EmacPsInstancePtr)), &BdTemplate, XEMACPS_RECV); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap ("Error setting up RxBD space, BdRingClone"); return XST_FAILURE; } /* * Setup TxBD space. * * Like RxBD space, we have already defined a properly aligned area * of memory to use. * * Also like the RxBD space, we create a template. Notice we don't * set the "last" attribute. The example will be overriding this * attribute so it does no good to set it up here. */ XEmacPs_BdClear(&BdTemplate); XEmacPs_BdSetStatus(&BdTemplate, XEMACPS_TXBUF_USED_MASK); /* * Create the TxBD ring */ Status = XEmacPs_BdRingCreate(&(XEmacPs_GetTxRing (EmacPsInstancePtr)), TX_BD_LIST_START_ADDRESS, TX_BD_LIST_START_ADDRESS, XEMACPS_BD_ALIGNMENT, TXBD_CNT); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap ("Error setting up TxBD space, BdRingCreate"); return XST_FAILURE; } Status = XEmacPs_BdRingClone(&(XEmacPs_GetTxRing(EmacPsInstancePtr)), &BdTemplate, XEMACPS_SEND); if (Status != XST_SUCCESS) { EmacPsUtilErrorTrap ("Error setting up TxBD space, BdRingClone"); return XST_FAILURE; } /* * Set emacps to phy loopback */ #ifndef PEEP /* For Zynq board */ XEmacPs_SetMdioDivisor(EmacPsInstancePtr, MDC_DIV_224); sleep(1); #endif EmacPsUtilEnterLoopback(EmacPsInstancePtr, EMACPS_LOOPBACK_SPEED_1G); XEmacPs_SetOperatingSpeed(EmacPsInstancePtr, EMACPS_LOOPBACK_SPEED_1G); /* * Setup the interrupt controller and enable interrupts */ Status = EmacPsSetupIntrSystem(IntcInstancePtr, EmacPsInstancePtr, EmacPsIntrId); /* * Run the EmacPs DMA Single Frame Interrupt example */ Status = EmacPsDmaSingleFrameIntrExample(EmacPsInstancePtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Disable the interrupts for the EmacPs device */ EmacPsDisableIntrSystem(IntcInstancePtr, EmacPsIntrId); /* * Stop the device */ XEmacPs_Stop(EmacPsInstancePtr); return XST_SUCCESS; }