/**
*
* This function returns the IRQ Type of a given GPIO pin.
*
* @param InstancePtr is a pointer to an XGpioPs instance.
* @param Pin is the pin number whose IRQ type is to be obtained.
* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
*
* @return None.
*
* @note Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
* returned by this function.
*
*****************************************************************************/
u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, int Pin)
{
u32 IntrType;
u32 IntrPol;
u32 IntrOnAny;
u8 Bank;
u8 PinNumber;
u8 IrqType;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
/*
* Get the Bank number and Pin number within the bank.
*/
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET) & PinNumber;
IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET) & PinNumber;
IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET) & PinNumber;
if (IntrType == 1) {
if (IntrOnAny == 1) {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
} else if (IntrPol == 1) {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
} else {
IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
}
} else {
if (IntrPol == 1) {
IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
} else {
IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
}
}
return IrqType;
}
/**
*
* This function clears the specified pending interrupt. This function should be
* called after the software has serviced the interrupts that are pending.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the interrupt status is to be
* cleared. Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, int Pin)
{
u8 Bank;
u8 PinNumber;
u32 IntrReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
/*
* Get the Bank number and Pin number within the bank.
*/
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
/*
* Clear the specified pending interrupts.
*/
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET);
IntrReg &= (1 << Pin);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET, IntrReg);
}
/**
*
* Set the Output Enable of the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number to which the Data is to be written.
* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
* @param OpEnable specifies whether the Output Enable for the specified
* pin should be enabled.
* Valid values are 0 for Disabling Output Enable,
* 1 for Enabling Output Enable.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, int Pin, int OpEnable)
{
u8 Bank;
u8 PinNumber;
u32 OpEnableReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
Xil_AssertVoid((OpEnable == 0) || (OpEnable == 1));
/*
* Get the Bank number and Pin number within the bank.
*/
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET);
if (OpEnable) { /* Enable Output Enable */
OpEnableReg |= (1 << PinNumber);
} else { /* Disable Output Enable */
OpEnableReg &= ~ (1 << PinNumber);
}
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_OUTEN_OFFSET, OpEnableReg);
}
/**
*
* Set the Direction of the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number to which the Data is to be written.
* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
* @param Direction is the direction to be set for the specified pin.
* Valid values are 0 for Input Direction, 1 for Output Direction.
*
* @return None.
*
*****************************************************************************/
void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, int Pin, int Direction)
{
u8 Bank;
u8 PinNumber;
u32 DirModeReg;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
Xil_AssertVoid((Direction == 0) || (Direction == 1));
/*
* Get the Bank number and Pin number within the bank.
*/
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET);
if (Direction) { /* Output Direction */
DirModeReg |= (1 << PinNumber);
} else { /* Input Direction */
DirModeReg &= ~ (1 << PinNumber);
}
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_DIRM_OFFSET, DirModeReg);
}
/**
*
* This function returns interrupt status read from Interrupt Status Register.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
*
* @return The value read from Interrupt Status Register.
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
{
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET);
}
/**
*
* This function is used for getting the Interrupt Type, Interrupt Polarity and
* Interrupt On Any for the specified GPIO Bank pins.
*
* @param InstancePtr is a pointer to an XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
* @param IntrType returns the 32 bit mask of the interrupt type.
* 0 means Level Sensitive and 1 means Edge Sensitive.
* @param IntrPolarity returns the 32 bit mask of the interrupt
* polarity. 0 means Active Low or Falling Edge and 1 means
* Active High or Rising Edge.
* @param IntrOnAny returns the 32 bit mask of the interrupt trigger for
* edge triggered interrupts. 0 means trigger on single edge using
* the configured interrupt polarity and 1 means trigger on both
* edges.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
u32 *IntrPolarity, u32 *IntrOnAny)
{
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Bank < XGPIOPS_MAX_BANKS);
*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET);
*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET);
*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET);
}
/**
*
* This function returns the interrupt enable status for a bank.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Bank is the bank number of the GPIO to operate on.
* Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
*
* @return Enabled interrupt(s) in a 32-bit format. Bit positions with 1
* indicate that the interrupt for that pin is enabled, bit
* positions with 0 indicate that the interrupt for that pin is
* disabled.
*
* @note None.
*
*****************************************************************************/
u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
{
u32 IntrMask;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Bank < XGPIOPS_MAX_BANKS);
IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTMASK_OFFSET);
return ~IntrMask;
}
/**
*
* This function returns interrupt enable status of the specified pin.
*
* @param InstancePtr is a pointer to the XGpioPs instance.
* @param Pin is the pin number for which the interrupt enable status
* is to be known.
* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
*
* @return
* - TRUE if the interrupt has occurred.
* - FALSE if the interrupt has not occurred.
*
* @note None.
*
*****************************************************************************/
int XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, int Pin)
{
u8 Bank;
u8 PinNumber;
u32 IntrReg;
Xil_AssertNonvoid(InstancePtr != NULL);
Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertNonvoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
/*
* Get the Bank number and Pin number within the bank.
*/
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTSTS_OFFSET);
return (IntrReg & (1 << Pin)) ? TRUE : FALSE;
}
/**
*
* This function is used for setting the IRQ Type of a single GPIO pin.
*
* @param InstancePtr is a pointer to an XGpioPs instance.
* @param Pin is the pin number whose IRQ type is to be set.
* Valid values are 0 to XGPIOPS_DEVICE_MAX_PIN_NUM - 1.
* @param IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
* defined in xgpiops.h to specify the IRQ type.
*
* @return None.
*
* @note None.
*
*****************************************************************************/
void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, int Pin, u8 IrqType)
{
u32 IntrTypeReg;
u32 IntrPolReg;
u32 IntrOnAnyReg;
u8 Bank;
u8 PinNumber;
Xil_AssertVoid(InstancePtr != NULL);
Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
Xil_AssertVoid(Pin < XGPIOPS_DEVICE_MAX_PIN_NUM);
Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
/*
* Get the Bank number and Pin number within the bank.
*/
XGpioPs_GetBankPin(Pin, &Bank, &PinNumber);
IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET);
IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET);
IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET);
switch (IrqType) {
case XGPIOPS_IRQ_TYPE_EDGE_RISING:
IntrTypeReg |= (1 << PinNumber);
IntrPolReg |= (1 << PinNumber);
IntrOnAnyReg &= ~(1 << PinNumber);
break;
case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
IntrTypeReg |= (1 << PinNumber);
IntrPolReg &= ~(1 << PinNumber);
IntrOnAnyReg &= ~(1 << PinNumber);
break;
case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
IntrTypeReg |= (1 << PinNumber);
IntrOnAnyReg |= (1 << PinNumber);
break;
case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
IntrTypeReg &= ~(1 << PinNumber);
IntrPolReg |= (1 << PinNumber);
break;
case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
IntrTypeReg &= ~(1 << PinNumber);
IntrPolReg &= ~(1 << PinNumber);
break;
}
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTPOL_OFFSET, IntrPolReg);
XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
((Bank) * XGPIOPS_REG_MASK_OFFSET) +
XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
}
