コード例 #1
0
ファイル: bootm.c プロジェクト: Analias/SNOWLeo-SDR-1
int do_bootb_kintex7(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	u32 FrameBuffer[8];
    u32 BootAddress = simple_strtoul(argv[1], NULL, 16);
	u32 Index = 0;
    u32 Count;
    
    if (argc < 2)
		return -1;
    
    if ((BootAddress <  CONFIG_SYS_FLASH_BASE) || (BootAddress > (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)))
    {
        return -1;
    }

    /*
	 * Create the data to be written to the ICAP.
	 */
	FrameBuffer[Index++] = XHI_DUMMY_PACKET;
	FrameBuffer[Index++] = XHI_SYNC_PACKET;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;
    FrameBuffer[Index++] = 0x30020001;                        /* Type 1 write to WBSTAR */
    FrameBuffer[Index++] = BootAddress;
    FrameBuffer[Index++] = 0x30008001;                        /* Type 1 Write to CMD */
    FrameBuffer[Index++] = XHI_CMD_IPROG;
	FrameBuffer[Index++] = XHI_NOOP_PACKET;

     /*
	  * Fill the FIFO with as many words as it will take (or as many as we have to send).
	  */
	while(Index > XHwIcap_GetWrFifoVacancy(HWICAP_BASEADDR));
	for (Count = 0; Count < Index; Count++)
    {
    	XHwIcap_FifoWrite(HWICAP_BASEADDR, FrameBuffer[Count]);
	}

    /*
	 * Start the transfer of the data from the FIFO to the ICAP device.
	 */
	XHwIcap_StartConfig(HWICAP_BASEADDR);

	while ((XHwIcap_ReadReg(HWICAP_BASEADDR,XHI_CR_OFFSET)) & XHI_CR_WRITE_MASK);
    
	while (XHwIcap_IsDeviceBusy(HWICAP_BASEADDR) != 0);
	while (XHwIcap_ReadReg(HWICAP_BASEADDR, XHI_CR_OFFSET) & XHI_CR_WRITE_MASK);
    
    /* The code should never get here sice the FPGA should reset */
    return -1;
}
コード例 #2
0
ファイル: xhwicap_intr.c プロジェクト: flynnjs/embeddedsw
/**
*
* The interrupt handler for HwIcap interrupts. This function must be connected
* by the user to an interrupt source.
*
* @param	InstancePtr is a pointer to the XHwIcap instance.
*
* @return	None.
*
* @note		The interrupts are being used only while writing data to the
*		ICAP device. The reading of the data from the ICAP device is
*		done in polled mode.
*		In a worst case scenario the interrupt handler can
*		be busy writing large amount of data to the Write FIFO.
*
******************************************************************************/
void XHwIcap_IntrHandler(void *InstancePtr)
{
	XHwIcap *HwIcapPtr = (XHwIcap *) InstancePtr;
	u32 IntrStatus;
	u32 WrFifoVacancy;


	Xil_AssertVoid(InstancePtr != NULL);


	/*
	 * Get the Interrupt status.
	 */
	IntrStatus = XHwIcap_IntrGetStatus(HwIcapPtr);

	if (IntrStatus & XHI_IPIXR_WRP_MASK) {

		/*
		 * A transmit has just completed. Check for more data
		 * to transmit.
		 */
		if (HwIcapPtr->RemainingWords > 0) {

			/*
			 * Fill the FIFO with as many words as it will take (or
			 * as many as we have to write). We can use the Write
			 * FIFO vacancy to know if the device can take more data.
			 */
			WrFifoVacancy = XHwIcap_GetWrFifoVacancy(HwIcapPtr);
			while ((WrFifoVacancy != 0) &&
			       (HwIcapPtr->RemainingWords > 0)) {
				XHwIcap_FifoWrite(HwIcapPtr,
						*HwIcapPtr->SendBufferPtr);

				HwIcapPtr->RemainingWords--;
				WrFifoVacancy--;
				HwIcapPtr->SendBufferPtr++;
			}

			XHwIcap_StartConfig(HwIcapPtr);
		}
		else {

			if (HwIcapPtr->RequestedWords != 0) {

				/*
				 * No more data to send. Disable the interrupts
				 * by disabling the Global Interrupts.
				 * Inform the upper layer software that the
				 * transfer is done.
				 */
				XHwIcap_IntrGlobalDisable(HwIcapPtr);
				HwIcapPtr->IsTransferInProgress = FALSE;
				HwIcapPtr->StatusHandler(HwIcapPtr->StatusRef,
						    XST_HWICAP_WRITE_DONE,
						    HwIcapPtr->RequestedWords);
			}
		}
	}


	/*
	 * Clear the Interrupt status.
	 */
	XHwIcap_IntrClear(HwIcapPtr, IntrStatus);

}