コード例 #1
0
// Enable interrupts by using a simple interrupt routine. If more complex
// interrupt routine is needed, you must create your own interrupt handler routine.
void sound_initInterupts()
{
	microblaze_register_handler(sound_interrupt_handler, NULL);
	XIntc_EnableIntr(XPAR_INTC_0_BASEADDR, XPAR_AXI_AC97_0_INTERRUPT_MASK);
	XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
	microblaze_enable_interrupts();
}
コード例 #2
0
ファイル: platform.c プロジェクト: vsiva/sp605-lwip
void platform_setup_interrupts()
{
	XIntc *intcp;
	intcp = &intc;

	XIntc_Initialize(intcp, XPAR_XPS_INTC_0_DEVICE_ID);
	XIntc_Start(intcp, XIN_REAL_MODE);

	/* Start the interrupt controller */
	XIntc_MasterEnable(XPAR_XPS_INTC_0_BASEADDR);

#ifdef __PPC__
	Xil_ExceptionInit();
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
			(XExceptionHandler)XIntc_DeviceInterruptHandler,
			(void*) XPAR_XPS_INTC_0_DEVICE_ID);
#elif __MICROBLAZE__
	microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);
#endif

	platform_setup_timer();

#ifdef XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK
	/* Enable timer and EMAC interrupts in the interrupt controller */
	XIntc_EnableIntr(XPAR_XPS_INTC_0_BASEADDR,
#ifdef __MICROBLAZE__
			PLATFORM_TIMER_INTERRUPT_MASK |
#endif
			XPAR_ETHERNET_MAC_IP2INTC_IRPT_MASK);
#endif
}
コード例 #3
0
ファイル: interrupt_driver.c プロジェクト: gravufo/INF3995
void init_interrupt_controller()
{
	XIntc *intcp;
	intcp = &intc;

	XIntc_Initialize(intcp, XPAR_INTC_0_DEVICE_ID);
	XIntc_Start(intcp, XIN_REAL_MODE);

	// Démarrage du gestionnaire d'interruption
	XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);

	microblaze_register_handler((XInterruptHandler)XIntc_InterruptHandler, intcp);

	// Configuration spécifique au core présent dans le système
	init_network_timer_int();
	init_ps2_int();
	init_sound_int();
	init_display_timer_int();

	XIntc_Enable(intcp, XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR);
	XIntc_Enable(intcp, XPAR_XPS_INTC_0_PS2CORE_0_PS2_INTERRUPT_INTR);
	XIntc_Enable(intcp, XPAR_XPS_INTC_0_PLB_AC97_0_INTERRUPT_INTR);
	XIntc_Enable(intcp, XPAR_INTC_0_LLTEMAC_0_VEC_ID);

	//XIntc_SetIntrSvcOption(XPAR_INTC_0_BASEADDR,/*XIN_SVC_ALL_ISRS_OPTION*/XIN_SVC_SGL_ISR_OPTION);
}
コード例 #4
0
void initInterrupts()
{
	microblaze_register_handler(interrupt_handler_dispatcher, NULL);
	XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
			(XPAR_FIT_TIMER_0_INTERRUPT_MASK
		   | XPAR_DMA_CONTROLLER_0_INTERRUPT_MASK));
	XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
	microblaze_enable_interrupts();
}
コード例 #5
0
void interrupts_init() {
	microblaze_register_handler(interrupt_handler_dispatcher, NULL);
	// Enable interrupts from FIT, GPIO block, and AC97
	XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
		(XPAR_FIT_TIMER_0_INTERRUPT_MASK | XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK
				| XPAR_AXI_AC97_0_INTERRUPT_MASK));
	XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);

	microblaze_enable_interrupts();
}
コード例 #6
0
void start_intc(void) {
  
  // Setting Interupt controller
    xil_printf("\r\nSetting up Interrupt Controller:\r\n");

  //Initialize exception handling
    xil_printf("     Initialize exception handling\r\n");
  microblaze_enable_exceptions();
  
  // Register external interrupt handler
    xil_printf("     Register external interrupt handler\r\n");
  microblaze_register_handler((XInterruptHandler)XIntc_DeviceInterruptHandler,
                            (void *)XPAR_XPS_INTC_0_DEVICE_ID);
 
//  // Register UART interrupt handler
//  //  xil_printf("     Register UART interrupt handler\r\n");
//  XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,XPAR_INTC_0_RS232_INTERRUPT_INTR,
//      (XInterruptHandler)uart_int_handler,(void *)XPAR_RS232_BASEADDR);

  // Register OPB_FX2 interrupt handler
    xil_printf("     Register I2C_SLAVE interrupt handler\r\n");
  XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR,XPAR_XPS_INTC_0_XPS_I2C_SLAVE_0_IP2INTC_IRPT_INTR,
      (XInterruptHandler)i2c_slave_int_handler,(void *)XPAR_XPS_I2C_SLAVE_0_BASEADDR);

  // Enable timer interrupts
//  //  xil_printf("     Register OPB_TIMER interrupt handler\r\n");
//	XIntc_mMasterEnable(XPAR_OPB_TIMER_0_BASEADDR);  // Start the interrupt controller
//	XIntc_SetIntrSvcOption( XPAR_INTC_0_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);

  // Enable uart interrupt in the interrupt controller
    xil_printf("     Enable interrupts in the interrupt controller\r\n");
  XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
//                    XPAR_RS232_INTERRUPT_MASK | 
//							XPAR_XPS_TIMER_0_INTERRUPT_MASK |
//							XPAR_OPB_FX2_0_INTERRUPT_MASK |
						  XPAR_XPS_I2C_SLAVE_0_IP2INTC_IRPT_MASK);

    xil_printf("     Start the interrupt controller\r\n");
  XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);

  // Enable uart interrupts
//  //  xil_printf("     Enable uart interrupt in Uartlite\r\n");
//  XUartLite_mEnableIntr(XPAR_RS232_BASEADDR);
  
//  xil_printf("     Enable all interrupts in XPS_FX2\r\n");
					
  // Enable MB interrupts
  //  xil_printf("     Enable MB interrupts\r\n");
  microblaze_enable_interrupts();
}
コード例 #7
0
ファイル: interrupts.c プロジェクト: YazanHalawa/ECEn-427
int interruptManager (unsigned int * framePointer0) {
	init_platform();
	// Initialize the GPIO peripherals.
	int success;

	// Used for CPU utilization. Uncomment if desired
	// XTmrCtr_Initialize(instPtr, 0);

	success = XGpio_Initialize(&gpPB, XPAR_PUSH_BUTTONS_5BITS_DEVICE_ID);
	// Set the push button peripheral to be inputs.
	XGpio_SetDataDirection(&gpPB, 1, 0x0000001F);
	// Enable the global GPIO interrupt for push buttons.
	XGpio_InterruptGlobalEnable(&gpPB);
	// Enable all interrupts in the push button peripheral.
	XGpio_InterruptEnable(&gpPB, 0xFFFFFFFF);

	// Reset the XAC97 Chip
	XAC97_HardReset(XPAR_AXI_AC97_0_BASEADDR);
	XAC97_mSetControl(XPAR_AXI_AC97_0_BASEADDR, AC97_ENABLE_IN_FIFO_INTERRUPT);
	XAC97_mSetControl(AC97_ExtendedAudioStat, AC97_EXTENDED_AUDIO_CONTROL_VRA);
	setVolLevel(AC97_VOL_MAX);
	clearAllSounds();

	microblaze_register_handler(interrupt_handler_dispatcher, NULL);
	XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
			(XPAR_FIT_TIMER_0_INTERRUPT_MASK | XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK | XPAR_AXI_AC97_0_INTERRUPT_MASK));
	XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
	microblaze_enable_interrupts();

	// Uncomment for CPU utilization stats
	/*XTmrCtr Timer;
	XTmrCtr *instPtr = &Timer;
	XTmrCtr_Initialize(instPtr, 0);
	XTmrCtr_Start(instPtr, 0);*/
	while(!isEndOfGame()); // Program never ends.

	// Uncomment for CPU utilization stats
	/*XTmrCtr_Stop(instPtr, 0);
	int val = (int) XTmrCtr_GetValue(instPtr, 0);
	xil_printf("%d\n\r", val);*/
	clearAllSounds();
	XAC97_ClearFifos(XPAR_AXI_AC97_0_BASEADDR);
	drawGameOver();
	cleanup_platform();

	return 0;
}
コード例 #8
0
ファイル: hal_aux.c プロジェクト: EPiCS/reconos_v2
//----------------------------------------------------------------------------
// Interrupt support
void
hal_platform_IRQ_init(void)
{
// We need first to have a decent decoding routine!
    XINTC_PPC_WRITE(XINTC_PPC_CIE,XINTC_PPC_ALL);
    XINTC_PPC_WRITE(XINTC_PPC_IAR,XINTC_PPC_ALL);
#ifndef CYGPKG_REDBOOT
    // This is a write-once bit, so if we are not planning to enable
    // interrupts at this time, we can safely delay this to a later time
#ifdef XIntc_mMasterEnable
    XIntc_mMasterEnable(UPBHWR_INTC_0_BASEADDR);
#else
#ifdef XIntc_MasterEnable
    XIntc_MasterEnable(UPBHWR_INTC_0_BASEADDR);
#endif
#endif
#endif
}
コード例 #9
0
void initInterrupts()
{
	// Initialize the GPIO peripherals. NOTE: We wait to do this till after the HDMI to ensure that nothing happens before the HDMI is enabled.
	XGpio_Initialize(&gpPB, XPAR_PUSH_BUTTONS_5BITS_DEVICE_ID);
	// Set the push button peripheral to be inputs.
	XGpio_SetDataDirection(&gpPB, 1, 0x0000001F);

	XGpio_Initialize(&gpswitches, XPAR_SLIDE_SWITCHES_8BITS_DEVICE_ID);
	XGpio_SetDataDirection(&gpswitches, 1, 0x000000FF);

	microblaze_register_handler(interrupt_handler_dispatcher, NULL);
	XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
			(XPAR_PIT_0_INTERRUPT_MASK
		   | XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK
		   | XPAR_AXI_AC97_0_INTERRUPT_MASK
		   | XPAR_PS2CTRL_0_INTERRUPT_MASK));

	XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
	microblaze_enable_interrupts();
}
コード例 #10
0
//--------------------------------------------------------------------
// PowerPC Timer Initialization functions.
//	For PowerPC, DEC and opb_timer can be used for Profiling. This
//	is selected by the user in standalone BSP
//
//--------------------------------------------------------------------
int powerpc405_init(void)
{
	Xil_ExceptionInit();
	Xil_ExceptionDisableMask( XIL_EXCEPTION_NON_CRITICAL ) ;

	// Initialize the Timer.
	// 1. If PowerPC DEC Timer has to be used, initialize DEC timer.
	// 2. Else use opb_timer. It can be directly connected or thru intc to PowerPC
#ifdef PPC_PIT_INTERRUPT
	ppc_dec_init();
#else
#ifdef TIMER_CONNECT_INTC
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_NON_CRITICAL_INT,
				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);

	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
			     (XInterruptHandler)profile_intr_handler,(void*)0);
#else
	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
			      (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
	Xil_ExceptionRegisterHandler( XIL_EXCEPTION_ID_NON_CRITICAL_INT,
			      (Xil_ExceptionHandler)profile_intr_handler,(void *)0);
#endif
	// Initialize the timer with Timer Ticks
	opb_timer_init() ;
#endif

	// Enable Interrupts in the System, if Profile Timer is the only Interrupt
	// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef PPC_PIT_INTERRUPT
	XTime_DECEnableInterrupt() ;
#elif TIMER_CONNECT_INTC
	XIntc_MasterEnable( INTC_BASEADDR );
	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
#endif
	Xil_ExceptionEnableMask( XEXC_NON_CRITICAL ) ;
#endif
	return 0;
}
コード例 #11
0
ファイル: main.c プロジェクト: parkerpatriot/space-invaders
int main (void) {
    init_platform();
    // Initialize the GPIO peripherals.
    XGpio_Initialize(&gpPB, XPAR_PUSH_BUTTONS_5BITS_DEVICE_ID);
    // Set the push button peripheral to be inputs.
    XGpio_SetDataDirection(&gpPB, 1, 0x0000001F);
    // Enable the global GPIO interrupt for push buttons.
    XGpio_InterruptGlobalEnable(&gpPB);
    // Enable all interrupts in the push button peripheral.
    XGpio_InterruptEnable(&gpPB, 0xFFFFFFFF);

    pit_init();
    pit_load_value(1000000); // init to 10 ms
    pit_enable_load();
    pit_enable_interrupts();
    pit_enable_count();


    microblaze_register_handler(interrupt_handler_dispatcher, NULL);
    XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
    		(XPAR_PIT_0_MYINTERRUPT_MASK | XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK));
    XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);

    microblaze_enable_interrupts();

    // Tell stdin that it gets zero! none! (as far as buffering goes)
    setvbuf(stdin, NULL, _IONBF, 0);

    while(1){
		// blocking call: wait until a character is present
		char input = getchar();

		// Handle the UART control of game
		uartControl_handle(input);
    }

    cleanup_platform();

    return 0;
}
コード例 #12
0
//--------------------------------------------------------------------
// Initialize the Profile Timer for MicroBlaze Target.
//	For MicroBlaze, opb_timer is used. The opb_timer can be directly
//	connected to MicroBlaze or connected through Interrupt Controller.
//
//--------------------------------------------------------------------
int microblaze_init(void)
{
	// Register profile_intr_handler
	// 1. If timer is connected to Interrupt Controller, register the handler
	//    to Interrupt Controllers vector table.
	// 2. If timer is directly connected to MicroBlaze, register the handler
	//    as Interrupt handler
	Xil_ExceptionInit();

#ifdef TIMER_CONNECT_INTC
	XIntc_RegisterHandler( INTC_BASEADDR, PROFILE_TIMER_INTR_ID,
			     (XInterruptHandler)profile_intr_handler,(void*)0);
#else
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
				     (Xil_ExceptionHandler)profile_intr_handler,
				     (void *)0) ;
#endif

	// Initialize the timer with Timer Ticks
	opb_timer_init() ;

	// Enable Interrupts in the System, if Profile Timer is the only Interrupt
	// in the System.
#ifdef ENABLE_SYS_INTR
#ifdef TIMER_CONNECT_INTC
	XIntc_MasterEnable( INTC_BASEADDR );
	XIntc_SetIntrSvcOption( INTC_BASEADDR, XIN_SVC_ALL_ISRS_OPTION);
	XIntc_EnableIntr( INTC_BASEADDR, PROFILE_TIMER_INTR_MASK );
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
				     (Xil_ExceptionHandler)XIntc_DeviceInterruptHandler,(void *)0);
#endif

#endif

	Xil_ExceptionEnable();

	return 0;

}
コード例 #13
0
void interrupts_init() {
    microblaze_register_handler(interrupt_handler_dispatcher, NULL);
    // Enable interrupts from FIT, GPIO block, and AC97
//	XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
//		(XPAR_FIT_TIMER_0_INTERRUPT_MASK | XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK
//				| XPAR_AXI_AC97_0_INTERRUPT_MASK));

    // Enable interrupts from the PIT, GPIO block, and AC97
    XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
                     (XPAR_PIT_0_MYINTERRUPT_MASK | XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK
                      | XPAR_AXI_AC97_0_INTERRUPT_MASK | XPAR_DMA_CTRL_0_INTERRUPT_MASK));

    XAC97_mSetControl(XPAR_AXI_AC97_0_BASEADDR, AC97_ENABLE_IN_FIFO_INTERRUPT);
    XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);

    pit_load_value(1000000);
    pit_enable_load();
    pit_enable_count();
    pit_enable_interrupts();

    microblaze_enable_interrupts();
}
コード例 #14
0
ファイル: RealTimeClock.c プロジェクト: tymadsen/ECEN_427
int main (void) {
    init_platform();
    // Initialize the GPIO peripherals.
    int success;
    success = XGpio_Initialize(&gpPB, XPAR_PUSH_BUTTONS_5BITS_DEVICE_ID);
    // Set the push button peripheral to be inputs.
    XGpio_SetDataDirection(&gpPB, 1, 0x0000001F);
    // Enable the global GPIO interrupt for push buttons.
    XGpio_InterruptGlobalEnable(&gpPB);
    // Enable all interrupts in the push button peripheral.
    XGpio_InterruptEnable(&gpPB, 0xFFFFFFFF);

    microblaze_register_handler(interrupt_handler_dispatcher, NULL);
    XIntc_EnableIntr(XPAR_INTC_0_BASEADDR,
    		(XPAR_FIT_TIMER_0_INTERRUPT_MASK | XPAR_PUSH_BUTTONS_5BITS_IP2INTC_IRPT_MASK));
    XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);
    microblaze_enable_interrupts();
 
    while(1);  // Program never ends.
 
    cleanup_platform();
 
    return 0;
}
コード例 #15
0
//---------------------------------------------------------------------------
//
// Function:    enableInterruptMaster
//
// Description: enables the interrupt master interrupt
//
// Parameters:  void
//
// Returns:     void
//
// State:
//
//---------------------------------------------------------------------------
void enableInterruptMaster(void)
{
    //enable global interrupt master
    XIntc_MasterEnable(XPAR_PCP_INTC_BASEADDR);
}
コード例 #16
0
int main()
{
  // Declare local variables and initialize global interrupt flag
  
   
  
  Xuint32 i,j, numElements, numElementsParallel,temp1,temp2,slv_reg0;
  Xuint32 DT_PeriphAddr, DT_InputRAM_AddrBase, DT_OutputRAM_AddrBase,DT_CoeffRAM_AddrBase;
  
  DT_PeriphAddr = XPAR_DECISIONTREECLEAN_0_BASEADDR;
  DT_InputRAM_AddrBase = XPAR_DECISIONTREECLEAN_0_MEM0_BASEADDR;
  DT_OutputRAM_AddrBase = XPAR_DECISIONTREECLEAN_0_MEM1_BASEADDR;
  DT_CoeffRAM_AddrBase = XPAR_DECISIONTREECLEAN_0_MEM2_BASEADDR;
  volatile Xuint32 calcVal, temp, pseudo_intr;
  
 
  interrupt_flag = 0;
  
  ////////////////////////////
  // INTERRUPT INITIALIZATION
  ////////////////////////////
  
//  // Initialize Interrupts on Microblaze
 Xil_ExceptionInit();

//  // Register the interrupt handler of the XPS Interrupt Controller with the Microblaze external interrupt
  Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT, (XExceptionHandler)XIntc_DeviceInterruptHandler, 
   (void *)XPAR_INTC_0_DEVICE_ID);

//  // Register the DECISIONTREECLEAN interrupt handler in the vector table of the XPS Interrupt Controller
 XIntc_RegisterHandler(XPAR_INTC_0_BASEADDR, XPAR_XPS_INTC_0_DECISIONTREECLEAN_0_IP2INTC_IRPT_INTR, 
    (XInterruptHandler)DECISIONTREECLEAN_Intr_DefaultHandler, (void *)XPAR_DECISIONTREECLEAN_0_BASEADDR);

//  // Start the XPS Interrupt Controller
  XIntc_MasterEnable(XPAR_INTC_0_BASEADDR);

//  // Enable DECISIONTREECLEAN interrupt requests in the XPS Interrupt Controller
  XIntc_EnableIntr(XPAR_INTC_0_BASEADDR, XPAR_DECISIONTREECLEAN_0_IP2INTC_IRPT_MASK);

//  // Local and global interrupt enable for the DECISIONTREECLEAN peripheral
  DECISIONTREECLEAN_EnableInterrupt((Xuint32 *) XPAR_DECISIONTREECLEAN_0_BASEADDR);

//  // Enable Microblaze non-critical (external) interrupts
  Xil_ExceptionEnable();
  

  ////////////////////////////
  // MAIN PROGRAM FUNCTIONS
  ////////////////////////////
  
  // prepare the lookup table 
  
  
    DECISIONTREECLEAN_mWriteSlaveReg2(DT_PeriphAddr, 0, 0xffffffff); //for the RAM_ACCESS WE-- slv_reg2(31)
	 
//Write the LUK UP tables
 
    for (j=0; j< 8; j++)
        {

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4), 0x00010006 ); //00010000000000000110 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(16*4),0x00000C06); //00000000110000000110 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(16*4+4),0x00023411); //00100011010000010001 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(32*4),0x00000C06); //00000000110000000110 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(32*4+4), 0x00000C00); //00000000110000000000 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(32*4+8),0x50004131); //01010100000100110001 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(32*4+12),0x00033C11); //00110011110000010001 );
        
        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4),0x00000C06); //00000000110000000110 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+4),0x00020C00); //00100000110000000000 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+8), 0x00000C00); //00000000110000000000 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+12), 0x00033C11); //00110011110000010001 );
        
        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+16), 0x40004D31); //01000100110100110001 );

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+20),0x000BA00F ); //10111010000000001111);

        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+24),0x00000000 ); //00000000000000000000 );
        
        DECISIONTREECLEAN_mWriteMemory(DT_CoeffRAM_AddrBase+(j*64*4)+(48*4+28), 0x00000000); //00000000000000000000 );

        }
//   for ( i =0 ; i<19; i++)
//	   {
//	 temp1 =DECISIONTREECLEAN_mReadMemory(DT_CoeffRAM_AddrBase+i*4);
//	  printf("coeff_mem %lu\n", temp1);
//	   }
	 DECISIONTREECLEAN_mWriteSlaveReg2(DT_PeriphAddr, 0, 0x00000000); //for the RAM_ACCESS WE-- slv_reg2(31)
	 

	 
  // Store the number of xyz samples we are going to process - do this for compatibility

	scanf("%lu", &numElements);
  
  // First loop stores all xyz samples into the source buffer

	for (i=0; i < numElements; i++)
  {
		scanf("%x", &temp);
    DECISIONTREECLEAN_mWriteMemory(DT_InputRAM_AddrBase + i*4, temp);// written to the memory controller
	}
	
//	temp2 =DECISIONTREECLEAN_mReadMemory(DT_InputRAM_AddrBase);
//	 printf("input_ram=%lu\n", temp2);
  
  // Wait for a bit for LabView to catch up
  
  //for (i=0; i < 10000; i++);
  
  // Set up the DECISIONTREECLEAN module
  
  
  numElementsParallel = ceil(numElements / 8) - 1;
  
  DECISIONTREECLEAN_mWriteSlaveReg1(DT_PeriphAddr, 0, numElementsParallel);
  
  // Start the DECISIONTREECLEAN module processing the samples
  
  DECISIONTREECLEAN_mWriteSlaveReg0(DT_PeriphAddr, 0, 0x1); // go bit
//  slv_reg0= DECISIONTREECLEAN_mReadSlaveReg0(DT_PeriphAddr, 0);
//  printf("slv_reg0 %lu\n", slv_reg0);  
   //printf("we reached before interrupt");
  
  // Wait for DECISIONTREECLEAN to finish
  
  while (interrupt_flag == 0);
  
//  pseudo_intr= DECISIONTREECLEAN_mReadSlaveReg5(DT_PeriphAddr, 0);
//  printf("psi-%lu\n",pseudo_intr);
    
  // After completion of operations, store the calculation time required and clear counter
  //if (pseudo_intr == 1 )
  //{
  //printf("we reached after interrupt\n");
  calcVal = DECISIONTREECLEAN_mReadSlaveReg7(DT_PeriphAddr, 0);
  DECISIONTREECLEAN_mWriteSlaveReg6(DT_PeriphAddr, 0, 0xffffffff);
  
  // Transmit results of calculation, plus the count value from the calculation timer
  
  temp = numElements + 1;
    
  printf("%u\n", temp);

	for (i=0; i < (numElementsParallel+1); i++) {
    temp = DECISIONTREECLEAN_mReadMemory(DT_OutputRAM_AddrBase + i*4);
		printf("%u\n", temp);
	}
  
  printf("%u\n", calcVal);
  //}
	return 0;
}
コード例 #17
0
int main (void)
{
   XGpio dip;
   int dip_check;


   static XPs2 Ps2Inst;
   XPs2_Config *ConfigPtr;
   u32 StatusReg;
   u32 BytesReceived;
   u8 RxBuffer;
   int key_count=0;
   int i;

   status=PVP;
   int x_cur=7, y_cur=7, x_pos=0, y_pos=0;

   XGpio_Initialize(&dip, XPAR_DIP_SWITCHES_8BITS_DEVICE_ID);
   XGpio_SetDataDirection(&dip, 1, 0xffffffff);

   ConfigPtr = XPs2_LookupConfig(XPAR_XPS_PS2_0_0_DEVICE_ID);
   XPs2_CfgInitialize(&Ps2Inst, ConfigPtr, ConfigPtr->BaseAddress);

   XIntc_RegisterHandler(XPAR_XPS_INTC_0_BASEADDR,
   		                 XPAR_XPS_INTC_0_XPS_TIMER_0_INTERRUPT_INTR,
                         (XInterruptHandler) timer_int_handler,
                         (void *)XPAR_XPS_TIMER_0_BASEADDR);

   XIntc_MasterEnable(XPAR_XPS_INTC_0_BASEADDR);
   XIntc_EnableIntr(XPAR_XPS_INTC_0_BASEADDR, 0x1);

   XTmrCtr_SetLoadReg(XPAR_XPS_TIMER_0_BASEADDR, 0, 333333);

   XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_INT_OCCURED_MASK | XTC_CSR_LOAD_MASK );

   XIntc_EnableIntr(XPAR_XPS_TIMER_0_BASEADDR, XPAR_XPS_TIMER_0_INTERRUPT_MASK);

   XTmrCtr_SetControlStatusReg(XPAR_XPS_TIMER_0_BASEADDR, 0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK |
     						XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK);

   microblaze_enable_interrupts();

   InitializeGame(x_cur, y_cur);status=PVP;

   xil_printf("-- Game Starts! --\r\n");
   xil_printf("\r\nHuman Player's turn!\r\n");

   int vga_input;
   vga_input=(0<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(1<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(2<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(3<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(4<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(5<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(6<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(7<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(8<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(0<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);

   vga_input=(0<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(1<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(2<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(3<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(4<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(5<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(6<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(7<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(8<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);

     vga_input=(0<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(1<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(2<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(3<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(4<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(5<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(6<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(7<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(8<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
     vga_input=(9<<24)+(29<<16)+(1<<8)+3;
     VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);

   vga_input=(0<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(1<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(2<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(3<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(4<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(5<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(6<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(7<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(8<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);

   vga_input=(9<<24)+(1<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(2<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(3<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(4<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(5<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(6<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(7<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(8<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(9<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(10<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);

   vga_input=(9<<24)+(11<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(12<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(13<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(14<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(15<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(16<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(17<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(18<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(19<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(20<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);

   vga_input=(9<<24)+(21<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(22<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(23<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(24<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(25<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(26<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(27<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(28<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(29<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);
   vga_input=(9<<24)+(30<<16)+(1<<8)+3;
   VGA_IP_mWriteReg(XPAR_VGA_IP_0_BASEADDR, 0, vga_input);


   while (1)
   {
	  if (turn==HUMAN_PLAYER || (turn==COMPUTER_PLAYER && status==PVP)) {
		  do {
			  if (turn==COMPUTER_PLAYER && status==PVC)
			  	  break;
		      dip_check=XGpio_DiscreteRead(&dip, 1);
	          StatusReg = XPs2_GetStatus(&Ps2Inst);
	      }while((StatusReg & XPS2_STATUS_RX_FULL) == 0);
	      BytesReceived = XPs2_Recv(&Ps2Inst, &RxBuffer, 1);
	      key_count=(key_count+1)%3;
	      if (key_count==0) {
	    	  if (RxBuffer==0x21&& win_flag==0) {
	    		  DrawNumber(level,3,2,EMPTY);

	    		  if(level==1)
	    			  level=2;
	    		  else
	    			  level=1;

	    		  if(status==PVC )
	    		  DrawNumber(level,3,2,0);
	    		  else if(status==CVP)
			      DrawNumber(level,3,2,1);
	    		  else
	    		  DrawNumber(level,3,2,EMPTY);

	    	  }
		      if (RxBuffer==0x1D && win_flag==0) {
			      EraseCursor(x_cur, y_cur);
		          if (y_cur<=0)
		    	      y_cur=14;
		          else
		    	      y_cur--;
		          DrawChess(x_cur, y_cur, CURSOR);
		      }
		      if (RxBuffer==0x1B && win_flag==0) {
		  	      EraseCursor(x_cur, y_cur);
		  	      if (y_cur>=14)
		  	          y_cur=0;
		  	      else
		  	          y_cur++;
		  	      DrawChess(x_cur, y_cur, CURSOR);
		      }
		      if (RxBuffer==0x1C && win_flag==0) {
		  	      EraseCursor(x_cur, y_cur);
		  	      if (x_cur<=0)
		  	          x_cur=14;
		  	      else
		  		      x_cur--;
		  	      DrawChess(x_cur, y_cur, CURSOR);
		      }
		      if (RxBuffer==0x23 && win_flag==0) {
		  	      EraseCursor(x_cur, y_cur);
		  	      if (x_cur>=14)
		  	          x_cur=0;
		  	      else
		  		      x_cur++;
		  	      DrawChess(x_cur, y_cur, CURSOR);
		      }
		      if (RxBuffer==0x5A && win_flag==0) {
		    	  DrawBack(3,1119,EMPTY);
			      if (board_state[x_cur][y_cur]==EMPTY) {

			  	      if(status==CVP)
				      DrawChess(x_cur, y_cur, 1-turn);
			  	      else
			  	      DrawChess(x_cur, y_cur, turn);

				      board_state[x_cur][y_cur]=turn;
				      board_record[BackTimes].x=x_cur;
				      board_record[BackTimes].y=y_cur;
				      BackTimes++;
				      count=0;
				      time0=0;
				      if (turn==COMPUTER_PLAYER)
				    	  step_flag=1;
				      if (CheckWin(x_cur,y_cur,turn)==1) {
					      xil_printf("\r\nHuman Player wins!\r\n");
					      win_flag=1;
					      DrawWinning(0, 1, EMPTY);
					      if(status==CVP)
						      DrawWinning(0, 1, 1-turn);
					      else
					          DrawWinning(0, 1, turn);
				      }
				      if (CheckBan(x_cur,y_cur,turn)==1){
				    	  xil_printf("\r\nComputer Player wins!\r\n");
				    	  win_flag=1;
				    	  DrawWinning(0, 1, EMPTY);
					      if(status==CVP)
						      DrawWinning(0, 1, turn);
					      else
					          DrawWinning(0, 1, 1-turn);
				      }
				      else {
				    	  if (turn==HUMAN_PLAYER)
				    		  turn=COMPUTER_PLAYER;
				    	  else
				    		  turn=HUMAN_PLAYER;
				          xil_printf("\r\nComputer Player's turn!\r\n");
				      }
			      }
			  }
		      if (RxBuffer==0x29 && turn==HUMAN_PLAYER && win_flag==0) {
		    	  count=0;time0=0;

		    	  if (status==PVP) {
			    	  x_cur=7;
			    	  y_cur=7;
			    	  for (i=0; i<256; i++) {
			    	  		board_record[i].x=0;
			    	  	    board_record[i].y=0;
			    	  			  }
				      InitializeGame(x_cur, y_cur);status=PVP;
		    		  DrawStatus(1, 21, EMPTY,status);
		    		  status=PVC;
		    		  DrawNumber(level,3,2,0);
		    		  DrawStatus(1, 21, COMPUTER_PLAYER,status);
		    	  }
		    	  else if(status==PVC) {
			    	  x_cur=7;
			    	  y_cur=7;
			    	  for (i=0; i<256; i++) {
			    	  		board_record[i].x=0;
			    	  	    board_record[i].y=0;
			    	  			  }
				      InitializeGame(x_cur, y_cur);status=PVP;
		    		  DrawStatus(1, 21, EMPTY,status);
		    		  status=CVP;
		    		  DrawNumber(level,3,2,1);
		    		  DrawStatus(1, 21, COMPUTER_PLAYER,status);
		    		  turn=COMPUTER_PLAYER;
		    	  }
		    	  else if(status==CVP) {
			    	  x_cur=7;
			    	  y_cur=7;
			    	  for (i=0; i<256; i++) {
			    	  		board_record[i].x=0;
			    	  	    board_record[i].y=0;
			    	  			  }
				      InitializeGame(x_cur, y_cur);status=PVP;
		    		  DrawStatus(1, 21, EMPTY,status);
		    		  status=PVP;
		    		  DrawStatus(1, 21, COMPUTER_PLAYER,status);
		    	  }
		      }
		      if (RxBuffer==0x76) {
		    	  x_cur=7;
		    	  y_cur=7;
		    	  for (i=0; i<256; i++) {
		    	  		board_record[i].x=0;
		    	  	    board_record[i].y=0;
		    	  			  }
			      InitializeGame(x_cur, y_cur);status=PVP;
		      }
		      if (RxBuffer==0x2D) {
		      	  if(BackTimes>0){
		      		BackTimes--;
		      	  	x_cur=board_record[BackTimes].x;
		      	  	y_cur=board_record[BackTimes].y;
		      	  	board_state[x_cur][y_cur]=EMPTY;
		      	  	DrawChess(x_cur,y_cur,EMPTY);
		      	  	turn=1-turn;
		      	  	if(status==PVC)
		      	  	{
		      	  	BackTimes--;
		      	  	x_cur=board_record[BackTimes].x;
		      	  	y_cur=board_record[BackTimes].y;
		      	  	board_state[x_cur][y_cur]=EMPTY;
		      	  	DrawChess(x_cur,y_cur,EMPTY);
		      	  	turn=HUMAN_PLAYER;
		      	  	}
		      	    DrawBack(3,1119,turn);
		      	  					      }
		      	  				  		  }
	      }
	  }

	  if (turn==COMPUTER_PLAYER && (status==PVC ||status==CVP )&& win_flag==0) {
	      if (step_flag==0) {
	  		  if (x_cur-1<0)
	  			  x_pos=x_cur+1;
	  		  else
	  			  x_pos=x_cur-1;
	  		      y_pos=y_cur;
	  		      step_flag=1;
	      }
	  	  else {
	  		  if(level==2||level==3){
	  		  EvaluateComputerMove(board_state, 0, MIN_INFINITY, MAX_INFINITY, 0, 0);
	  		  x_pos=maxMoveX;
	  		  y_pos=maxMoveY;
	  		  xil_printf("\r\n computer \r\n");}
	  		  else
	  		  {
		  	  everyScore(Computer);
		  	  current_pos=best(Computer);
	  		  x_pos=current_pos.y;
	  		  y_pos=current_pos.x;
	  		  xil_printf("\r\n computer \r\n");
	  		  }

	  	  }
  	      xil_printf("\r\n%x, %x\r\n", x_pos, y_pos);

  	      if(status==CVP)
	      DrawChess(x_pos, y_pos, 1-turn);
  	      else
  	      DrawChess(x_pos, y_pos, turn);


	  	  board_state[x_pos][y_pos]=COMPUTER_PLAYER;
	  	  board_record[BackTimes].x=x_pos;
  		  board_record[BackTimes].y=y_pos;
  		  BackTimes++;

	  	  count=0;
	  	  time0=0;
	      if (CheckWin(x_pos, y_pos, turn)) {
	  	      xil_printf("\r\nComputer Player wins!\r\n");
	  	      win_flag=1;
	  	      DrawWinning(0,1, EMPTY);
	  	      if(status==CVP)
	  	    	  DrawWinning(0,1, 1-turn);
	  	      else
	  	    	  DrawWinning(0,1, turn);
	  	      turn=HUMAN_PLAYER;
	  	  }
	      else {
	    	  turn=HUMAN_PLAYER;
	    	  xil_printf("\r\nHuman Player's turn!\r\n");
	      }
	  }
   }
   return 0;
}
コード例 #18
0
int main()
{
    init_platform();
    //verbose = 1;

    xil_printf("\n\rLoading Sounds and initializing hardware...\n\r");

    loadWaveFiles();

    initializeAC97();

    xil_printf("Playing Sound\r\n");

    microblaze_enable_interrupts();
	microblaze_register_handler((XInterruptHandler) AC97_InterruptHandler, NULL);
	XAC97_mSetControl(XPAR_AXI_AC97_0_BASEADDR, AC97_ENABLE_IN_FIFO_INTERRUPT);
    XIntc_EnableIntr(XPAR_INTC_SINGLE_BASEADDR, XPAR_AXI_AC97_0_INTERRUPT_MASK);
    XIntc_MasterEnable(XPAR_INTC_SINGLE_BASEADDR);
    //xil_printf("Current Wave = %08x, CurrentAddress = %08x, CurrentStopAddress =%08x\r\n", CurrentWave, CurrentWave->ddrCurrentAddress, CurrentWave->ddrStopAddress );
    while(1){
        xil_printf("Please Select a Sound Effect (0-9)\r\n");
    	char ch;
    	read(0,&ch, 1);
    	switch(ch){
    	  case '0':
    		  playWaveFile(&DarthVader);
    		  break;
    	  case '1':
    		  playWaveFile(&BaseHit);
    		  break;
    	  case '2':
    		  playWaveFile(&InvHit);
    		  break;
    	  case '3':
    		  playWaveFile(&UFO);
    		  break;
    	  case '4':
    		  playWaveFile(&UFOHit);
    		  break;
    	  case '5':
    		  playWaveFile(&Shot);
    		  break;
    	  case '6':
    		  playWaveFile(&Walk1);
    		  break;
    	  case '7':
    		  playWaveFile(&Walk2);
    		  break;
    	  case '8':
    		  playWaveFile(&Walk3);
    		  break;
    	  case '9':
    		  playWaveFile(&Walk4);
    		  break;
    	}
    }
	//Xuint32 Current_Mode = Check_Initial_Mode (XPAR_QUAD_SPI_IF_0_BASEADDR);
    //u32 testResult = Quad_SPI_Flash_Test (XPAR_QUAD_SPI_IF_0_BASEADDR);
    //xil_printf("Quad_SPI_Flash Test Result %08X.\r\n", testResult);
    //u8 ReadByte =  Read_Flash_8(XPAR_QUAD_SPI_IF_0_BASEADDR, 0x00000000);
    //xil_printf("I read Byte %2X, from the SPI Flash.\r\n", ReadByte);
    //u32 FLASH_ID = Manufact_ID (XPAR_QUAD_SPI_IF_0_BASEADDR);
    //xil_printf("Flash ID is:  %08x.\r\n", FLASH_ID);
    //for(i = 0; i<256; i++){
    //   data[i]=i;
   // }

    //Page_Program (XPAR_QUAD_SPI_IF_0_BASEADDR, 2, Current_Mode, 2, 0, 256, data);

    //Fast_Read(XPAR_QUAD_SPI_IF_0_BASEADDR, 2, Current_Mode, 2, 0x00C00000, 256, 10, data1);
    //Fast_Read(XPAR_QUAD_SPI_IF_0_BASEADDR, 2, Current_Mode, 2, 0x00C00000, 256, 10, data2);
    //Page_Program (XPAR_QUAD_SPI_IF_0_BASEADDR, 2, Current_Mode, 2, 0, 256, data);
   // for(i = 0; i<256; i++){
   // 	xil_printf("%02x %02x\r\n", data1[i], data2[i]);
    //}
    //while(1) XAC97_WriteFifo(XPAR_AC97_PLB_CONTROLLER_0_BASEADDR, 0x0);
    //xil_printf("Final i: %d", i);
    cleanup_platform();

    return 0;
}