/** * * This function writes the GENFIFO entries to transmit the messages requested. * * @param InstancePtr is a pointer to the XQspiPsu instance. * @param Msg is a pointer to the structure containing transfer data. * @param Index of the current message to be handled. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if transfer fails. * - XST_DEVICE_BUSY if a transfer is already in progress. * * @note None. * ******************************************************************************/ static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, s32 Index) { u32 GenFifoEntry; u32 BaseAddress; u32 TempCount; u32 ImmData; #ifdef DEBUG xil_printf("\nXQspiPsu_GenFifoEntryData\r\n"); #endif BaseAddress = InstancePtr->Config.BaseAddress; GenFifoEntry = 0x0U; /* Bus width */ GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK); GenFifoEntry |= XQspiPsu_SelectSpiMode((u8)Msg[Index].BusWidth); GenFifoEntry |= InstancePtr->GenFifoCS; GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK); GenFifoEntry |= InstancePtr->GenFifoBus; /* Data */ if (((Msg[Index].Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE) { GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE; } else { GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE; } /* If Byte Count is less than 8 bytes do the transfer in IO mode */ if ((Msg[Index].ByteCount < 8U) && (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)) { InstancePtr->ReadMode = XQSPIPSU_READMODE_IO; XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) & ~XQSPIPSU_CFG_MODE_EN_MASK)); InstancePtr->IsUnaligned = 1; } XQspiPsu_TXRXSetup(InstancePtr, &Msg[Index], &GenFifoEntry); if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) { GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK); GenFifoEntry |= Msg[Index].ByteCount; #ifdef DEBUG xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry); #endif XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); } else { TempCount = Msg[Index].ByteCount; u32 Exponent = 8; /* 2^8 = 256 */ ImmData = TempCount & 0xFFU; /* Exponent entries */ GenFifoEntry |= XQSPIPSU_GENFIFO_EXP; while (TempCount != 0U) { if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != FALSE) { GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK); GenFifoEntry |= Exponent; #ifdef DEBUG xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry); #endif XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); } TempCount = TempCount >> 1; Exponent++; } /* Immediate entry */ GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_EXP); if ((ImmData & 0xFFU) != FALSE) { GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK); GenFifoEntry |= ImmData & 0xFFU; #ifdef DEBUG xil_printf("\nFifoEntry=%08x\r\n",GenFifoEntry); #endif XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); } } /* One dummy GenFifo entry in case of IO mode */ if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) && ((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) { GenFifoEntry = 0x0U; #ifdef DEBUG xil_printf("\nDummy FifoEntry=%08x\r\n",GenFifoEntry); #endif XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); } }
/** * * This function writes the GENFIFO entries to transmit the messages requested. * * @param InstancePtr is a pointer to the XQspiPsu instance. * @param Msg is a pointer to the structure containing transfer data. * @param Index of the current message to be handled. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if transfer fails. * - XST_DEVICE_BUSY if a transfer is already in progress. * * @note None. * ******************************************************************************/ static inline int XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg, int Index) { u32 GenFifoEntry; u32 BaseAddress; int TempCount; int ImmData; BaseAddress = InstancePtr->Config.BaseAddress; GenFifoEntry = 0x0; /* Bus width */ GenFifoEntry &= ~XQSPIPSU_GENFIFO_MODE_MASK; GenFifoEntry |= XQspiPsu_SelectSpiMode(Msg[Index].BusWidth); GenFifoEntry |= InstancePtr->GenFifoCS; GenFifoEntry &= ~XQSPIPSU_GENFIFO_BUS_MASK; GenFifoEntry |= InstancePtr->GenFifoBus; /* Data */ if (Msg[Index].Flags & XQSPIPSU_MSG_FLAG_STRIPE) GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE; else GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE; XQspiPsu_TXRXSetup(InstancePtr, &Msg[Index], &GenFifoEntry); if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) { GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK; GenFifoEntry |= Msg[Index].ByteCount; XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); } else { TempCount = Msg[Index].ByteCount; u32 Exponent = 8; /* 2^8 = 256 */ /* Check for ByteCount upper limit - 2^28 for DMA */ if (TempCount > XQSPIPSU_DMA_BYTES_MAX) { return XST_FAILURE; } ImmData = TempCount & 0xFF; /* Exponent entries */ GenFifoEntry |= XQSPIPSU_GENFIFO_EXP; while (TempCount != 0) { if (TempCount & XQSPIPSU_GENFIFO_EXP_START) { GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK; GenFifoEntry |= Exponent; XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); } TempCount = TempCount >> 1; Exponent++; } /* Immediate entry */ GenFifoEntry &= ~XQSPIPSU_GENFIFO_EXP; if (ImmData & 0xFF) { GenFifoEntry &= ~XQSPIPSU_GENFIFO_IMM_DATA_MASK; GenFifoEntry |= ImmData & 0xFF; XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry); } } return XST_SUCCESS; }