/** * * API to set high speed in card and host. Changes clock in host accordingly. * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; #if( ffconfigSDIO_DRIVER_USES_INTERRUPT == 0 ) u32 ulPollCount; #endif #ifndef MMC_CARD /* u32 ClockReg; */ #ifdef __ICCARM__ #pragma data_alignment = 32 u8 ReadBuff[64]; #pragma data_alignment = 4 #else u8 ReadBuff[64] __attribute__ ((aligned(32))); #endif u16 BlkCnt; u16 BlkSize; #endif Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); #ifndef MMC_CARD BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); Xil_DCacheFlushRange( ( unsigned )ReadBuff, 64); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_SET; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #if( ffconfigSDIO_DRIVER_USES_INTERRUPT != 0 ) StatusReg = XSdPs_WaitInterrupt( InstancePtr, XSDPS_INTR_ERR_MASK | XSDPS_INTR_TC_MASK ); if( ( StatusReg & XSDPS_INTR_TC_MASK ) != 0 ) { Status = XST_SUCCESS; } else { Status = XST_FAILURE; goto RETURN_PATH; } #else /* * Check for transfer complete * Polling for response * Limit the time spent here with a simpler counter 'ulPollCount' */ ulPollCount = 0; do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } ulPollCount++; if( ulPollCount == POLLCOUNT_MAX ) { Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); #endif /* ffconfigSDIO_DRIVER_USES_INTERRUPT */ /* * Change the clock frequency to 50 MHz */ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_50_MHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #else Arg = XSDPS_MMC_HIGH_SPEED_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #ifdef __arm__ usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #endif Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set high speed in card and host. Changes clock in host accordingly. * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; #ifndef MMC_CARD u32 ClockReg; u8 ReadBuff[64]; u16 BlkCnt; u16 BlkSize; #endif Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); #ifndef MMC_CARD BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); Xil_DCacheInvalidateRange(ReadBuff, 64); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_SET; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); /* * Change the clock frequency to 50 MHz */ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_50_MHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #else Arg = XSDPS_MMC_HIGH_SPEED_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #ifdef __arm__ usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #endif Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * Switches the SD card voltage from 3v3 to 1v8 * * * @param InstancePtr is a pointer to the XSdPs instance. * ******************************************************************************/ static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr) { s32 Status; u16 CtrlReg; u32 ReadReg; /* Send switch voltage command */ Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; } /* Wait for CMD and DATA line to go low */ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) { ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); } /* Stop the clock */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET); CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, CtrlReg); /* Wait minimum 5mSec */ #if defined (__arm__) || defined (__aarch64__) (void)usleep(5000U); #endif #ifdef __MICROBLAZE__ MB_Sleep(5U); #endif /* Enabling 1.8V in controller */ CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET); CtrlReg |= XSDPS_HC2_1V8_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET, CtrlReg); /* Start clock */ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Wait for CMD and DATA line to go high */ ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) != (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) { ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_PRES_STATE_OFFSET); } RETURN_PATH: return Status; }
/** * * Initialize Card with Identification mode sequence * * * @param InstancePtr is a pointer to the instance to be worked on. * * @return * - XST_SUCCESS if initialization was successful * - XST_FAILURE if failure - could be because * a) SD is already initialized * b) There is no card inserted * c) One of the steps (commands) in the * initialization cycle failed * * ******************************************************************************/ s32 XSdPs_CardInitialize(XSdPs *InstancePtr) { u8 Tmp; u32 Cnt; u32 PresentStateReg; u32 CtrlReg; u32 CSD[4]; #ifdef __ICCARM__ #pragma data_alignment = 32 static u8 ExtCsd[512]; #pragma data_alignment = 4 #else static u8 ExtCsd[512] __attribute__ ((aligned(32))); #endif u8 SCR[8] = { 0U }; u8 ReadBuff[64] = { 0U }; s32 Status; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); /* Default settings */ InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH; InstancePtr->CardType = XSDPS_CARD_SD; InstancePtr->Switch1v8 = 0U; InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ; if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) && ((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK) == XSDPS_CAPS_EMB_SLOT)) { InstancePtr->CardType = XSDPS_CHIP_EMMC; } else { Status = XSdPs_IdentifyCard(InstancePtr); if (Status == XST_FAILURE) { goto RETURN_PATH; } } if ((InstancePtr->CardType != XSDPS_CARD_SD) && (InstancePtr->CardType != XSDPS_CARD_MMC) && (InstancePtr->CardType != XSDPS_CHIP_EMMC)) { Status = XST_FAILURE; goto RETURN_PATH; } if (InstancePtr->CardType == XSDPS_CARD_SD) { Status = XSdPs_SdCardInitialize(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Change clock to default clock 25MHz */ InstancePtr->BusSpeed = SD_CLK_25_MHZ; Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else if ((InstancePtr->CardType == XSDPS_CARD_MMC) || (InstancePtr->CardType == XSDPS_CHIP_EMMC)) { Status = XSdPs_MmcCardInitialize(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Change clock to default clock 26MHz */ InstancePtr->BusSpeed = SD_CLK_26_MHZ; Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_Select_Card(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } if (InstancePtr->CardType == XSDPS_CARD_SD) { /* Pull-up disconnected during data transfer */ Status = XSdPs_Pullup(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_Get_BusWidth(InstancePtr, SCR); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) { Status = XSdPs_Change_BusWidth(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } if ((InstancePtr->Switch1v8 != 0U) && (InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) { /* Set UHS-I SDR104 mode */ Status = XSdPs_Uhs_ModeInit(InstancePtr, XSDPS_UHS_SPEED_MODE_SDR104); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else { /* * card supports CMD6 when SD_SPEC field in SCR register * indicates that the Physical Layer Specification Version * is 1.10 or later. So for SD v1.0 cmd6 is not supported. */ if (SCR[0] != 0U) { /* Get speed supported by device */ Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Check for high speed support */ if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } } } } else if (((InstancePtr->CardType == XSDPS_CARD_MMC) && (InstancePtr->Card_Version > CSD_SPEC_VER_3)) && (InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) { Status = XSdPs_Change_BusWidth(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) { Status = XST_FAILURE; goto RETURN_PATH; } } } else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){ /* Change bus width to 8-bit */ Status = XSdPs_Change_BusWidth(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* Get Extended CSD */ Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] & (EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 | EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) { Status = XSdPs_Change_BusSpeed(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) { Status = XST_FAILURE; goto RETURN_PATH; } } } Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } RETURN_PATH: return Status; }
/** * * Initializes a specific XSdPs instance such that the driver is ready to use. * * * @param InstancePtr is a pointer to the XSdPs instance. * @param ConfigPtr is a reference to a structure containing information * about a specific SD device. This function initializes an * InstancePtr object for a specific device specified by the * contents of Config. * @param EffectiveAddr is the device base address in the virtual memory * address space. The caller is responsible for keeping the address * mapping from EffectiveAddr to the device physical base address * unchanged once this function is invoked. Unexpected errors may * occur if the address mapping changes after this function is * called. If address translation is not used, use * ConfigPtr->Config.BaseAddress for this device. * * @return * - XST_SUCCESS if successful. * - XST_DEVICE_IS_STARTED if the device is already started. * It must be stopped to re-initialize. * * @note This function initializes the host controller. * Initial clock of 400KHz is set. * Voltage of 3.3V is selected as that is supported by host. * Interrupts status is enabled and signal disabled by default. * Default data direction is card to host and * 32 bit ADMA2 is selected. Defualt Block size is 512 bytes. * ******************************************************************************/ s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, u32 EffectiveAddr) { s32 Status; u8 PowerLevel; u8 ReadReg; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(ConfigPtr != NULL); /* Set some default values. */ InstancePtr->Config.BaseAddress = EffectiveAddr; InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz; InstancePtr->IsReady = XIL_COMPONENT_IS_READY; InstancePtr->Config.CardDetect = ConfigPtr->CardDetect; InstancePtr->Config.WriteProtect = ConfigPtr->WriteProtect; /* Disable bus power */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_POWER_CTRL_OFFSET, 0U); /* Delay to poweroff card */ #if defined (__arm__) || defined (__aarch64__) (void)sleep(1U); #endif #ifdef __MICROBLAZE__ MB_Sleep(1000U); #endif /* "Software reset for all" is initiated */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET, XSDPS_SWRST_ALL_MASK); /* Proceed with initialization only after reset is complete */ ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET); while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) { ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET); } /* Host Controller version is read. */ InstancePtr->HC_Version = (u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK); /* * Read capabilities register and update it in Instance pointer. * It is sufficient to read this once on power on. */ InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_CAPS_OFFSET); /* Select voltage and enable bus power. */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_POWER_CTRL_OFFSET, XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK); /* Change the clock frequency to 400 KHz */ Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH ; } if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) { PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK; } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) { PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK; } else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) { PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK; } else { PowerLevel = 0U; } /* Select voltage based on capability and enable bus power. */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_POWER_CTRL_OFFSET, PowerLevel | XSDPS_PC_BUS_PWR_MASK); /* Enable ADMA2 in 64bit mode. */ XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, XSDPS_HC_DMA_ADMA2_32_MASK); /* Enable all interrupt status except card interrupt initially */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_EN_OFFSET, XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK)); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_EN_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); /* Disable all interrupt signals by default. */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U); /* * Transfer mode register - default value * DMA enabled, block count enabled, data direction card to host(read) */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK); /* Set block size to 512 by default */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK); Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set high speed in card and host. Changes clock in host accordingly. * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ int XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { u32 Status = 0; u32 StatusReg = 0x0; u32 Arg = 0; #ifndef MMC_CARD u32 ClockReg; u8 ReadBuff[64]; u16 BlkCnt; u16 BlkSize; #endif Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); #ifndef MMC_CARD BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_SET; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if (StatusReg & XSDPS_INTR_ERR_MASK) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET); ClockReg &= ~(XSDPS_CC_INT_CLK_EN_MASK | XSDPS_CC_SD_CLK_EN_MASK); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, ClockReg); ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET); ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK); ClockReg |= XSDPS_CC_SDCLK_FREQ_BASE_MASK | XSDPS_CC_INT_CLK_EN_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, ClockReg); /* * Wait for internal clock to stabilize */ while((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET) & XSDPS_CC_INT_CLK_STABLE_MASK) == 0); /* * Enable SD clock */ ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET, ClockReg | XSDPS_CC_SD_CLK_EN_MASK); StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #else Arg = XSDPS_MMC_HIGH_SPEED_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } usleep(XSDPS_MMC_DELAY_FOR_SWITCH); XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET,StatusReg); Status = XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); #endif Status = XST_SUCCESS; RETURN_PATH: return Status; }
/** * * API to set high speed in card and host. Changes clock in host accordingly. * * * @param InstancePtr is a pointer to the XSdPs instance. * * @return * - XST_SUCCESS if successful. * - XST_FAILURE if fail. * * @note None. * ******************************************************************************/ s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr) { s32 Status; u32 StatusReg; u32 Arg; u32 ClockReg; u16 BlkCnt; u16 BlkSize; u8 ReadBuff[64]; Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); if (InstancePtr->CardType == XSDPS_CARD_SD) { BlkCnt = XSDPS_SWITCH_CMD_BLKCNT; BlkSize = XSDPS_SWITCH_CMD_BLKSIZE; BlkSize &= XSDPS_BLK_SIZE_MASK; XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET, BlkSize); XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff); Xil_DCacheFlushRange((INTPTR)ReadBuff, 64); XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET, XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK); Arg = XSDPS_SWITCH_CMD_HS_SET; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete * Polling for response for now */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); /* Change the clock frequency to 50 MHz */ InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ; Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else if (InstancePtr->CardType == XSDPS_CARD_MMC) { Arg = XSDPS_MMC_HIGH_SPEED_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); /* Change the clock frequency to 52 MHz */ InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ; Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } } else { Arg = XSDPS_MMC_HS200_ARG; Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } /* * Check for transfer complete */ do { StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET); if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) { /* * Write to clear error bits */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK); Status = XST_FAILURE; goto RETURN_PATH; } } while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U); /* * Write to clear bit */ XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK); /* Change the clock frequency to 200 MHz */ InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK; Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } Status = XSdPs_Execute_Tuning(InstancePtr); if (Status != XST_SUCCESS) { Status = XST_FAILURE; goto RETURN_PATH; } #if defined (__arm__) || defined (__aarch64__) /* Program the Tap delays */ XSdPs_SetTapDelay(InstancePtr); #endif } #if defined (__arm__) || defined (__aarch64__) usleep(XSDPS_MMC_DELAY_FOR_SWITCH); #endif #ifdef __MICROBLAZE__ /* 2 msec delay */ MB_Sleep(2); #endif StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET); StatusReg |= XSDPS_HC_SPEED_MASK; XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg); Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress, XSDPS_RESP0_OFFSET); Status = XST_SUCCESS; RETURN_PATH: return Status; }