/*
*
* Runs an internal loopback test on the SPI device. This is done as a master
* with a enough data to fill the FIFOs if FIFOs are present. If the device is
* configured as a slave-only, this function returns successfully even though
* no loopback test is performed.
*
* This function does not restore the device context after performing the test
* as it assumes the device will be reset after the call.
*
* @param InstancePtr is a pointer to the XSpi instance to be worked on.
*
* @return
* - XST_SUCCESS if loopback was performed successfully or not
* performed at all if device is slave-only.
* - XST_LOOPBACK_ERROR if loopback failed.
*
* @note None.
*
******************************************************************************/
static int LoopbackTest(XSpi *InstancePtr)
{
u32 StatusReg;
u32 ControlReg;
u32 Index;
u32 Data;
u32 RxData;
u32 NumSent = 0;
u32 NumRecvd = 0;
u8 DataWidth;
/*
* Cannot run as a slave-only because we need to be master in order to
* initiate a transfer. Still return success, though.
*/
if (InstancePtr->SlaveOnly) {
return XST_SUCCESS;
}
/*
* Setup the control register to enable master mode and the loopback so
* that data can be sent and received.
*/
ControlReg = XSpi_GetControlReg(InstancePtr);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_LOOPBACK_MASK | XSP_CR_MASTER_MODE_MASK);
/*
* We do not need interrupts for this loopback test.
*/
XSpi_IntrGlobalDisable(InstancePtr);
DataWidth = InstancePtr->DataWidth;
/*
* Send data up to the maximum size of the transmit register, which is
* one byte without FIFOs. We send data 4 times just to exercise the
* device through more than one iteration.
*/
for (Index = 0; Index < 4; Index++) {
Data = 0;
/*
* Fill the transmit register.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
while ((StatusReg & XSP_SR_TX_FULL_MASK) == 0) {
if (DataWidth == XSP_DATAWIDTH_BYTE) {
/*
* Data Transfer Width is Byte (8 bit).
*/
Data = 0;
} else if (DataWidth == XSP_DATAWIDTH_HALF_WORD) {
/*
* Data Transfer Width is Half Word (16 bit).
*/
Data = XSP_HALF_WORD_TESTBYTE;
} else if (DataWidth == XSP_DATAWIDTH_WORD){
/*
* Data Transfer Width is Word (32 bit).
*/
Data = XSP_WORD_TESTBYTE;
}
XSpi_WriteReg(InstancePtr->BaseAddr, XSP_DTR_OFFSET,
Data + Index);
NumSent += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
}
/*
* Start the transfer by not inhibiting the transmitter and
* enabling the device.
*/
ControlReg = XSpi_GetControlReg(InstancePtr) &
(~XSP_CR_TRANS_INHIBIT_MASK);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_ENABLE_MASK);
/*
* Wait for the transfer to be done by polling the transmit
* empty status bit.
*/
do {
StatusReg = XSpi_IntrGetStatus(InstancePtr);
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
XSpi_IntrClear(InstancePtr, XSP_INTR_TX_EMPTY_MASK);
/*
* Receive and verify the data just transmitted.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
while ((StatusReg & XSP_SR_RX_EMPTY_MASK) == 0) {
RxData = XSpi_ReadReg(InstancePtr->BaseAddr,
XSP_DRR_OFFSET);
if (DataWidth == XSP_DATAWIDTH_BYTE) {
if((u8)RxData != Index) {
return XST_LOOPBACK_ERROR;
}
} else if (DataWidth ==
XSP_DATAWIDTH_HALF_WORD) {
if((u16)RxData != (u16)(Index +
XSP_HALF_WORD_TESTBYTE)) {
return XST_LOOPBACK_ERROR;
}
} else if (DataWidth == XSP_DATAWIDTH_WORD) {
if(RxData != (u32)(Index + XSP_WORD_TESTBYTE)) {
return XST_LOOPBACK_ERROR;
}
}
NumRecvd += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
}
/*
* Stop the transfer (hold off automatic sending) by inhibiting
* the transmitter and disabling the device.
*/
ControlReg |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_SetControlReg(InstancePtr ,
ControlReg & ~ XSP_CR_ENABLE_MASK);
}
/*
* One final check to make sure the total number of bytes sent equals
* the total number of bytes received.
*/
if (NumSent != NumRecvd) {
return XST_LOOPBACK_ERROR;
}
return XST_SUCCESS;
}
/*
* Change LO frequency in integer mode
* frequency must be multiple of 40 (MHz)
*/
int trf3795changeFreqInt(XSpi *InstancePtr, u32 freq)
{
u32 StatusReg;
u32 ControlReg;
u32 Index;
u32 Delay;
u32 Data;
u32 NumSent = 0;
u32 NumRecvd = 0;
u32 RxData[] = {0,0,0};
u32 reg1Val, reg2Val, reg6Val;
u8 DataWidth;
u8 j;
int ctr;
u8 loDivSel, loDiv;
u8 pllDiv;
u8 pllDivSel;
u8 prscSel;
u16 rDiv;
u16 nInt;
// Calculate parameter and register values
freq = freq/2; // Output frequency is doubled
if(freq>2400)
{
loDiv = 1;
loDivSel = 0;
}
else if(freq>1200)
{
loDiv = 2;
loDivSel = 1;
}
else if(freq>600)
{
loDiv = 4;
loDivSel = 2;
}
else if(freq>300)
{
loDiv = 8;
loDivSel = 3;
}
pllDiv = (u8)ceil((double)loDiv*freq/3000.0);
//xil_printf("Pll Div %d\r\n", pllDiv);
rDiv = 1;
nInt = (u16)(loDiv*freq*rDiv/(10*pllDiv));
if(pllDiv==1)
pllDivSel = 0;
else if(pllDiv==2)
pllDivSel = 1;
else if(pllDiv==4)
pllDivSel = 2;
else
{
xil_printf("Invalid PLL_DIV!\r\n");
return XST_FAILURE;
}
if(nInt>=72)
prscSel = 1;
else
prscSel = 0;
//xil_printf("NInt %d\r\n", nInt);
//xil_printf("prscSel %d\r\n", prscSel);
//xil_printf("loDiv %d\r\n", loDiv);
reg1Val = XSP_REG1_WRITE_CF + (rDiv<<5);
reg2Val = XSP_REG2_WRITE_CF + (nInt<<5) + (pllDivSel<<21) + (prscSel<<23);
reg6Val = XSP_REG6_WRITE_CF + (loDivSel<<23);
u32 write_trf_register[] = {reg1Val,reg6Val,reg2Val};
u32 reg_list = {1,2,6};
//xil_printf("reg1: %x", reg1Val);
//xil_printf("reg2: %x", reg2Val);
//xil_printf("reg6: %x", reg6Val);
/*
* Setup the control reogister to enable master mode and
* to send least significant bit 1st
*/
ControlReg = XSpi_GetControlReg(InstancePtr);
XSpi_SetControlReg(InstancePtr, ControlReg | XSP_CR_MASTER_MODE_MASK |
XSP_CR_LSB_FIRST);
//xil_printf("ctrl reg setup done\r\n");
/*
* Set the slave select zero bit to active - low
*/
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFE);
/*
* We do not need interrupts for now
*/
XSpi_IntrGlobalDisable(InstancePtr);
DataWidth = InstancePtr->DataWidth;
/*****************************************************************************/
/*
* perform a write to a TRF3765 register
*/
for (Index = 0; Index < 3; Index++) { // for loop write to three registers
Data = 0;
xil_printf("start transfer %d\r\n", Index);
/*
* Fill the transmit register.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
//xil_printf("got status reg\r\n");
// while ((StatusReg & XSP_SR_TX_FULL_MASK) == 0) { // no loop, do just a single transfer for now
if (DataWidth == XSP_DATAWIDTH_BYTE) {
/*
* Data Transfer Width is Byte (8 bit).
*/
Data = 0;
} else if (DataWidth == XSP_DATAWIDTH_HALF_WORD) {
/*
* Data Transfer Width is Half Word (16 bit).
*/
Data = XSP_HALF_WORD_TESTBYTE;
} else if (DataWidth == XSP_DATAWIDTH_WORD){
/*
* Data Transfer Width is Word (32 bit).
*/
Data = write_trf_register[Index]; // choose the register index 0 to 7 ************
//xil_printf("selected register \r\n");
}
XSpi_WriteReg(InstancePtr->BaseAddr, XSP_DTR_OFFSET, Data);
//xil_printf("wrote data \r\n");
NumSent += (DataWidth >> 3);
//xil_printf("Numsent %d\r\n", NumSent);
StatusReg = XSpi_GetStatusReg(InstancePtr);
//xil_printf("status reg %d \r\n", StatusReg);
// }
/*
* Start the transfer by not inhibiting the transmitter and
* enabling the device.
*/
ControlReg = XSpi_GetControlReg(InstancePtr) &
(~XSP_CR_TRANS_INHIBIT_MASK);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_ENABLE_MASK);
/*
* Wait for the transfer to be done by polling the transmit
* empty status bit.
*/
//xil_printf("start for loop\r\n");
//xil_printf("status reg %d\r\n", XSpi_IntrGetStatus(InstancePtr));
ctr = 0;
do {
StatusReg = XSpi_IntrGetStatus(InstancePtr);
if(ctr > SPI_TIMEOUT)
break;
ctr++;
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
//xil_printf("done with while loop \r\n");
XSpi_IntrClear(InstancePtr, XSP_INTR_TX_EMPTY_MASK);
/*
* To create a latch enable pulse and extra read clock pulse,
* set the slave select one SS(1) bit low
*/
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFD); // creates read pulse and clock
for (Delay = 0; Delay < 10; Delay++) // more delay makes wider pulses
{}
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFF); // removes read pulse and clock
/*
* To create a latch enable pulse,
* set the slave select one SS(0) bit low
*/
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFE); // drives the latch enable
// for (Delay = 0; Delay < 10; Delay++) // more delay makes pulse wider
// {}
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFF); // removes the latch enable
/*
* Stop the transfer (hold off automatic sending) by inhibiting
* the transmitter and disabling the device.
*/
ControlReg |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_SetControlReg(InstancePtr ,
ControlReg & ~ XSP_CR_ENABLE_MASK);
//xil_printf("Done transfer %d\r\n", Index);
}
XSpi_Reset(InstancePtr);
return XST_SUCCESS;
}
/* Write to and read back the RF board TRF3795
*
*
******************************************************************************/
static int trf3795WriteAndRead(XSpi *InstancePtr)
{
u32 StatusReg;
u32 ControlReg;
u32 Index;
u32 Delay;
u32 Data;
u32 NumSent = 0;
u32 NumRecvd = 0;
u32 RxData[] = {0,0,0};
u8 DataWidth;
u8 j;
int ctr = 0;
u32 write_trf_register[] = {XSP_REG0_WRITE,XSP_REG1_WRITE,XSP_REG2_WRITE_ENC,XSP_REG3_WRITE,
XSP_REG4_WRITE,XSP_REG5_WRITE,XSP_REG6_WRITE, XSP_REG7_WRITE};
u32 read_trf_register[] = {XSP_REG0_READBACK,XSP_REG1_READBACK,XSP_REG2_READBACK,XSP_REG3_READBACK,
XSP_REG4_READBACK,XSP_REG5_READBACK,XSP_REG6_READBACK,XSP_REG7_READBACK,XSP_REG7_READBACK};
/*
* Setup the control register to enable master mode and
* to send least significant bit 1st
*/
ControlReg = XSpi_GetControlReg(InstancePtr);
XSpi_SetControlReg(InstancePtr, ControlReg | XSP_CR_MASTER_MODE_MASK |
XSP_CR_LSB_FIRST);
/*
* Set the slave select zero bit to active - low
*/
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFE);
/*
* We do not need interrupts for now
*/
XSpi_IntrGlobalDisable(InstancePtr);
DataWidth = InstancePtr->DataWidth;
/*****************************************************************************/
/*
* perform a write to a TRF3765 register
*/
for (Index = 0; Index < 8; Index++) { // for loop write to all eight registers
Data = 0;
/*
* Fill the transmit register.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
// while ((StatusReg & XSP_SR_TX_FULL_MASK) == 0) { // no loop, do just a single transfer for now
if (DataWidth == XSP_DATAWIDTH_BYTE) {
/*
* Data Transfer Width is Byte (8 bit).
*/
Data = 0;
} else if (DataWidth == XSP_DATAWIDTH_HALF_WORD) {
/*
* Data Transfer Width is Half Word (16 bit).
*/
Data = XSP_HALF_WORD_TESTBYTE;
} else if (DataWidth == XSP_DATAWIDTH_WORD){
/*
* Data Transfer Width is Word (32 bit).
*/
Data = write_trf_register[Index]; // choose the register index 0 to 7 ************
}
XSpi_WriteReg(InstancePtr->BaseAddr, XSP_DTR_OFFSET, Data);
NumSent += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
// }
/*
* Start the transfer by not inhibiting the transmitter and
* enabling the device.
*/
ControlReg = XSpi_GetControlReg(InstancePtr) &
(~XSP_CR_TRANS_INHIBIT_MASK);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_ENABLE_MASK);
/*
* Wait for the transfer to be done by polling the transmit
* empty status bit.
*/
//xil_printf("status reg %d \r\n", StatusReg);
//xil_printf("intr status reg %d \r\n", XSpi_IntrGetStatus(InstancePtr));
ctr = 0;
do {
StatusReg = XSpi_IntrGetStatus(InstancePtr);
if(ctr > SPI_TIMEOUT)
break;
ctr++;
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
XSpi_IntrClear(InstancePtr, XSP_INTR_TX_EMPTY_MASK);
/*
* To create a latch enable pulse and extra read clock pulse,
* set the slave select one SS(1) bit low
*/
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFD); // creates read pulse and clock
for (Delay = 0; Delay < 10; Delay++) // more delay makes wider pulses
{}
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFF); // removes read pulse and clock
/*
* To create a latch enable pulse,
* set the slave select one SS(0) bit low
*/
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFE); // drives the latch enable
// for (Delay = 0; Delay < 10; Delay++) // more delay makes pulse wider
// {}
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFF); // removes the latch enable
/*
* Stop the transfer (hold off automatic sending) by inhibiting
* the transmitter and disabling the device.
*/
ControlReg |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_SetControlReg(InstancePtr ,
ControlReg & ~ XSP_CR_ENABLE_MASK);
// } // end of the for loop
/*****************************************************************************/
/*
* To Read-back from the Internal Register Banks, Register 0 must be programmed
* with a specific command that sets the TRF3765 into read-back mode and
* specifies the register to be read
*/
// for (Index = 0; Index < 1; Index++) {
// Data = 0;
/*
* Fill the transmit register.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
// while ((StatusReg & XSP_SR_TX_FULL_MASK) == 0) { // do just a single transfer for now
if (DataWidth == XSP_DATAWIDTH_BYTE) {
/*
* Data Transfer Width is Byte (8 bit).
*/
Data = 0;
} else if (DataWidth == XSP_DATAWIDTH_HALF_WORD) {
/*
* Data Transfer Width is Half Word (16 bit).
*/
Data = XSP_HALF_WORD_TESTBYTE;
} else if (DataWidth == XSP_DATAWIDTH_WORD){
/*
* Data Transfer Width is Word (32 bit).
*/
Data = read_trf_register[Index]; // index of the register to readback here *********************
}
XSpi_WriteReg(InstancePtr->BaseAddr, XSP_DTR_OFFSET, Data);
NumSent += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
// }
/*
* Start the transfer by not inhibiting the transmitter and
* enabling the device.
*/
ControlReg = XSpi_GetControlReg(InstancePtr) &
(~XSP_CR_TRANS_INHIBIT_MASK);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_ENABLE_MASK); // | XSP_CR_CLK_PHASE_MASK);
/*
* Wait for the transfer to be done by polling the transmit
* empty status bit.
*/
ctr = 0;
do {
StatusReg = XSpi_IntrGetStatus(InstancePtr);
if(ctr > SPI_TIMEOUT)
break;
ctr++;
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
XSpi_IntrClear(InstancePtr, XSP_INTR_TX_EMPTY_MASK);
for (Delay = 0; Delay < 10; Delay++) // add delay
{}
/*
* To create a latch enable pulse and extra read clock pulse,
* set the slave select one SS(1) bit low
*/
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFD); // creates read pulse and clock
for (Delay = 0; Delay < 10; Delay++) // more delay makes wider pulses
{}
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFF); // removes read pulse and clock
for (Delay = 0; Delay < 10; Delay++) // add delay
{}
/*
* Stop the transfer (hold off automatic sending) by inhibiting
* the transmitter and disabling the device.
*/
ControlReg |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_SetControlReg(InstancePtr ,
ControlReg & ~ XSP_CR_ENABLE_MASK);
// } // end of the for loop
/*
************* Now read-back the specific register *********************************
*/
// for (Index = 0; Index < 1; Index++) {
// Data = 0;
/*
* Fill the transmit register.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
// while ((StatusReg & XSP_SR_TX_FULL_MASK) == 0) { // do just a single transfer for now
if (DataWidth == XSP_DATAWIDTH_BYTE) {
/*
* Data Transfer Width is Byte (8 bit).
*/
Data = 0;
} else if (DataWidth == XSP_DATAWIDTH_HALF_WORD) {
/*
* Data Transfer Width is Half Word (16 bit).
*/
Data = XSP_HALF_WORD_TESTBYTE;
} else if (DataWidth == XSP_DATAWIDTH_WORD){
/*
* Data Transfer Width is Word (32 bit).
*/
Data = XSP_ZERO_WRITE; // just leave the data bits at zero during read-back
}
XSpi_WriteReg(InstancePtr->BaseAddr, XSP_DTR_OFFSET,
Data + Index);
NumSent += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
// }
/*
* Start the transfer by not inhibiting the transmitter and
* enabling the device.
*/
ControlReg = XSpi_GetControlReg(InstancePtr) &
(~XSP_CR_TRANS_INHIBIT_MASK);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_ENABLE_MASK | XSP_CR_CLK_PHASE_MASK); // clock data in on the second edge (falling)
/*
* Wait for the transfer to be done by polling the transmit
* empty status bit.
*/
ctr = 0;
do {
StatusReg = XSpi_IntrGetStatus(InstancePtr);
if(ctr > SPI_TIMEOUT)
break;
ctr++;
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
XSpi_IntrClear(InstancePtr, XSP_INTR_TX_EMPTY_MASK);
/*
* Receive and verify the data just transmitted.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
while ((StatusReg & XSP_SR_RX_EMPTY_MASK) == 0) {
for (j = 0; j < 3; j++) {
RxData[j] = XSpi_ReadReg(InstancePtr->BaseAddr,
XSP_DRR_OFFSET);
NumRecvd += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
}
xil_printf("\r%08x\n\r", RxData[2]);
}
/*
* Stop the transfer (hold off automatic sending) by inhibiting
* the transmitter and disabling the device.
*/
ControlReg |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_SetControlReg(InstancePtr ,
ControlReg & ~ XSP_CR_ENABLE_MASK);
} // end of the for loop
/*
* One final check to make sure the total number of bytes sent equals
* the total number of bytes received.
*/
// if (NumSent != NumRecvd) {
// return XST_LOOPBACK_ERROR;
// }
xil_printf("\n\rTRF3765 Register Access Done\n\r");
return XST_SUCCESS;
}
/*
* Enables the fractional mode of the LO
* LO must be initialized first
*/
int trf3795EnableInt(XSpi *InstancePtr)
{
u32 StatusReg;
u32 ControlReg;
u32 Index;
u32 Delay;
u32 Data;
u32 NumSent = 0;
u32 NumRecvd = 0;
u32 RxData[] = {0,0,0};
u8 DataWidth;
u8 j;
int ctr;
u32 write_trf_register[] = {XSP_REG0_WRITE,XSP_REG1_WRITE,XSP_REG2_WRITE,XSP_REG3_WRITE,
XSP_REG4_WRITE,XSP_REG5_WRITE,XSP_REG6_WRITE,XSP_REG7_WRITE};
/*
* Setup the control reogister to enable master mode and
* to send least significant bit 1st
*/
ControlReg = XSpi_GetControlReg(InstancePtr);
XSpi_SetControlReg(InstancePtr, ControlReg | XSP_CR_MASTER_MODE_MASK |
XSP_CR_LSB_FIRST);
/*
* Set the slave select zero bit to active - low
*/
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFE);
/*
* We do not need interrupts for now
*/
XSpi_IntrGlobalDisable(InstancePtr);
DataWidth = InstancePtr->DataWidth;
/*****************************************************************************/
/*
* perform a write to a TRF3765 register
*/
for (Index = 0; Index < 8; Index++) { // for loop write to all eight registers
Data = 0;
/*
* Fill the transmit register.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
// while ((StatusReg & XSP_SR_TX_FULL_MASK) == 0) { // no loop, do just a single transfer for now
if (DataWidth == XSP_DATAWIDTH_BYTE) {
/*
* Data Transfer Width is Byte (8 bit).
*/
Data = 0;
} else if (DataWidth == XSP_DATAWIDTH_HALF_WORD) {
/*
* Data Transfer Width is Half Word (16 bit).
*/
Data = XSP_HALF_WORD_TESTBYTE;
} else if (DataWidth == XSP_DATAWIDTH_WORD){
/*
* Data Transfer Width is Word (32 bit).
*/
Data = write_trf_register[Index]; // choose the register index 0 to 7 ************
}
XSpi_WriteReg(InstancePtr->BaseAddr, XSP_DTR_OFFSET, Data);
NumSent += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
// }
/*
* Start the transfer by not inhibiting the transmitter and
* enabling the device.
*/
ControlReg = XSpi_GetControlReg(InstancePtr) &
(~XSP_CR_TRANS_INHIBIT_MASK);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_ENABLE_MASK);
/*
* Wait for the transfer to be done by polling the transmit
* empty status bit.
*/
do {
StatusReg = XSpi_IntrGetStatus(InstancePtr);
if(ctr > SPI_TIMEOUT)
break;
ctr++;
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
XSpi_IntrClear(InstancePtr, XSP_INTR_TX_EMPTY_MASK);
/*
* To create a latch enable pulse and extra read clock pulse,
* set the slave select one SS(1) bit low
*/
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFD); // creates read pulse and clock
for (Delay = 0; Delay < 10; Delay++) // more delay makes wider pulses
{}
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFF); // removes read pulse and clock
/*
* To create a latch enable pulse,
* set the slave select one SS(0) bit low
*/
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFE); // drives the latch enable
// for (Delay = 0; Delay < 10; Delay++) // more delay makes pulse wider
// {}
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFF); // removes the latch enable
/*
* Stop the transfer (hold off automatic sending) by inhibiting
* the transmitter and disabling the device.
*/
ControlReg |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_SetControlReg(InstancePtr ,
ControlReg & ~ XSP_CR_ENABLE_MASK);
}
XSpi_Reset(InstancePtr);
return XST_SUCCESS;
}
int trf3795ReadBackRegs(XSpi *InstancePtr)
{
u32 StatusReg;
u32 ControlReg;
u32 Index;
u32 Delay;
u32 Data;
u32 NumSent = 0;
u32 NumRecvd = 0;
u32 RxData[] = {0,0,0};
u8 DataWidth;
u8 j;
u32 read_trf_register[] = {XSP_REG0_READBACK,XSP_REG1_READBACK,XSP_REG2_READBACK,XSP_REG3_READBACK,
XSP_REG4_READBACK,XSP_REG5_READBACK,XSP_REG6_READBACK,XSP_REG7_READBACK};
ControlReg = XSpi_GetControlReg(InstancePtr);
XSpi_SetControlReg(InstancePtr, ControlReg | XSP_CR_MASTER_MODE_MASK |
XSP_CR_LSB_FIRST);
xil_printf("ctrl reg setup done\r\n");
/*
* Set the slave select zero bit to active - low
*/
// XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFE);
/*
* We do not need interrupts for now
*/
XSpi_IntrGlobalDisable(InstancePtr);
DataWidth = InstancePtr->DataWidth;
StatusReg = XSpi_GetStatusReg(InstancePtr);
for(Index=0; Index<8; Index++)
{
if (DataWidth == XSP_DATAWIDTH_BYTE) {
/*
* Data Transfer Width is Byte (8 bit).
*/
Data = 0;
} else if (DataWidth == XSP_DATAWIDTH_HALF_WORD) {
/*
* Data Transfer Width is Half Word (16 bit).
*/
Data = XSP_HALF_WORD_TESTBYTE;
} else if (DataWidth == XSP_DATAWIDTH_WORD){
/*
* Data Transfer Width is Word (32 bit).
*/
Data = read_trf_register[Index]; // index of the register to readback here *********************
}
XSpi_WriteReg(InstancePtr->BaseAddr, XSP_DTR_OFFSET, Data);
NumSent += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
/*
* Start the transfer by not inhibiting the transmitter and
* enabling the device.
*/
ControlReg = XSpi_GetControlReg(InstancePtr) &
(~XSP_CR_TRANS_INHIBIT_MASK);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_ENABLE_MASK); // | XSP_CR_CLK_PHASE_MASK);
/*
* Wait for the transfer to be done by polling the transmit
* empty status bit.
*/
//xil_printf("enter first tx while loop \r\n");
do {
StatusReg = XSpi_IntrGetStatus(InstancePtr);
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
XSpi_IntrClear(InstancePtr, XSP_INTR_TX_EMPTY_MASK);
for (Delay = 0; Delay < 10; Delay++) // add delay
{}
/*
* To create a latch enable pulse and extra read clock pulse,
* set the slave select one SS(1) bit low
*/
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFD); // creates read pulse and clock
for (Delay = 0; Delay < 10; Delay++) // more delay makes wider pulses
{}
XSpi_SetSlaveSelectReg(InstancePtr, 0xFFFF); // removes read pulse and clock
for (Delay = 0; Delay < 10; Delay++) // add delay
{}
/*
* Stop the transfer (hold off automatic sending) by inhibiting
* the transmitter and disabling the device.
*/
ControlReg |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_SetControlReg(InstancePtr ,
ControlReg & ~ XSP_CR_ENABLE_MASK);
// } // end of the for loop
/*
************* Now read-back the specific register *********************************
*/
// for (Index = 0; Index < 1; Index++) {
// Data = 0;
/*
* Fill the transmit register.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
// while ((StatusReg & XSP_SR_TX_FULL_MASK) == 0) { // do just a single transfer for now
if (DataWidth == XSP_DATAWIDTH_BYTE) {
/*
* Data Transfer Width is Byte (8 bit).
*/
Data = 0;
} else if (DataWidth == XSP_DATAWIDTH_HALF_WORD) {
/*
* Data Transfer Width is Half Word (16 bit).
*/
Data = XSP_HALF_WORD_TESTBYTE;
} else if (DataWidth == XSP_DATAWIDTH_WORD){
/*
* Data Transfer Width is Word (32 bit).
*/
Data = XSP_ZERO_WRITE; // just leave the data bits at zero during read-back
}
XSpi_WriteReg(InstancePtr->BaseAddr, XSP_DTR_OFFSET,
Data + Index);
NumSent += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
// }
/*
* Start the transfer by not inhibiting the transmitter and
* enabling the device.
*/
ControlReg = XSpi_GetControlReg(InstancePtr) &
(~XSP_CR_TRANS_INHIBIT_MASK);
XSpi_SetControlReg(InstancePtr, ControlReg |
XSP_CR_ENABLE_MASK | XSP_CR_CLK_PHASE_MASK); // clock data in on the second edge (falling)
/*
* Wait for the transfer to be done by polling the transmit
* empty status bit.
*/
//xil_printf("Enter tx empty while loop\r\n");
do {
StatusReg = XSpi_IntrGetStatus(InstancePtr);
} while ((StatusReg & XSP_INTR_TX_EMPTY_MASK) == 0);
XSpi_IntrClear(InstancePtr, XSP_INTR_TX_EMPTY_MASK);
/*
* Receive and verify the data just transmitted.
*/
StatusReg = XSpi_GetStatusReg(InstancePtr);
//xil_printf("Enter rx empty while loop\r\n");
while ((StatusReg & XSP_SR_RX_EMPTY_MASK) == 0) {
for (j = 0; j < 3; j++) {
RxData[j] = XSpi_ReadReg(InstancePtr->BaseAddr,
XSP_DRR_OFFSET);
NumRecvd += (DataWidth >> 3);
StatusReg = XSpi_GetStatusReg(InstancePtr);
}
xil_printf("\r%08x\n\r", RxData[2]);
}
/*
* Stop the transfer (hold off automatic sending) by inhibiting
* the transmitter and disabling the device.
*/
ControlReg |= XSP_CR_TRANS_INHIBIT_MASK;
XSpi_SetControlReg(InstancePtr ,
ControlReg & ~ XSP_CR_ENABLE_MASK);
} // end of the for loop
xil_printf("\n\rTRF3765 Register Access Done\n\r");
return XST_SUCCESS;
}
