inline void z80_port_write(uint16 PortNb, uint8 value) { //uint8 data = Value; //printf("z80_port_write PC=%04x OP=%02x p=%04x v=%02x\n",cpu_z80_get_pc(),memory.sm1[cpu_z80_get_pc()],PortNb,Value); switch (PortNb & 0xff) { case 0x4: YM2610_control_port_0_A_w(0, value); //data break; case 0x5: YM2610_data_port_0_A_w(0, value);//data break; case 0x6: YM2610_control_port_0_B_w(0, value);//data break; case 0x7: YM2610_data_port_0_B_w(0, value);//data break; case 0xC: result_code = value; break; default: break; } }
void PortWrite (UINT16 PortNo, UINT8 data) { switch (PortNo & 0xff) { case 0x4: YM2610_control_port_0_A_w (0, data); break; case 0x5: YM2610_data_port_0_A_w (0, data); break; case 0x6: YM2610_control_port_0_B_w (0, data); break; case 0x7: YM2610_data_port_0_B_w (0, data); break; case 0x8: /* NMI enable / acknowledge? (the data written doesn't matter) */ break; case 0xc: result_code = data; break; case 0x18: /* NMI disable? (the data written doesn't matter) */ break; case 0x80: cdda_stop (); break; default: //printf("Unimplemented Z80 Write Port: %x data: %x\n",PortNo&0xff,data); break; } }
void mame_z80_writeport16(uint16 PortNo, uint8 data) #endif { //printf ("write _port_ %x _data_ %x \n",(PortNo & 0xff), data); switch( PortNo & 0xff) { case 0x4: YM2610_control_port_0_A_w(0,data); break; case 0x5: YM2610_data_port_0_A_w(0,data); break; case 0x6: YM2610_control_port_0_B_w(0,data); break; case 0x7: YM2610_data_port_0_B_w(0,data); break; case 0x8: /* NMI enable / acknowledge? (the data written doesn't matter) */ break; case 0xc: result_code = data; break; case 0x18: /* NMI disable? (the data written doesn't matter) */ break; default: //printf("Unimplemented Z80 Write Port: %x data: %x\n",PortNo&0xff,data); break; } }