/* FIXME: put comments here */
void rtems_exception_init_mngt(void)
{
ISR_Level level;
_CPU_ISR_Disable(level);
_CPU_ISR_install_vector(ARM_EXCEPTION_UNDEF,
_Exception_Handler_Undef_Swi,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_SWI,
_Exception_Handler_Undef_Swi,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_PREF_ABORT,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_DATA_ABORT,
_exc_data_abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_FIQ,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_install_vector(ARM_EXCEPTION_IRQ,
_Exception_Handler_Abort,
NULL);
_CPU_ISR_Enable(level);
}
int
m860_char_poll_read (int minor)
{
unsigned char c;
rtems_unsigned32 level;
_CPU_ISR_Disable(level);
if (RxBd[minor]->status & M860_BD_EMPTY) {
_CPU_ISR_Enable(level);
return -1;
}
c = ((char *)RxBd[minor]->buffer)[0];
RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP;
_CPU_ISR_Enable(level);
return c;
}
void __ISR_Handler(uint32_t vector, CPU_Interrupt_frame *ifr)
{
register uint32_t level;
_exception_stack_frame = NULL;
/* Interrupts are disabled upon entry to this Handler */
_Thread_Dispatch_disable_level++;
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if ( _ISR_Nest_level == 0 ) {
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high - 4;
}
#endif
_ISR_Nest_level++;
if ( _ISR_Vector_table[ vector] )
{
(*_ISR_Vector_table[ vector ])(vector, ifr);
};
/* Make sure that interrupts are disabled again */
_CPU_ISR_Disable( level );
_ISR_Nest_level--;
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if( _ISR_Nest_level == 0)
stack_ptr = _old_stack_ptr;
#endif
_Thread_Dispatch_disable_level--;
_CPU_ISR_Enable( level );
if ( _ISR_Nest_level )
return;
if ( _Thread_Dispatch_disable_level ) {
_ISR_Signals_to_thread_executing = FALSE;
return;
}
if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
_ISR_Signals_to_thread_executing = FALSE;
/* save off our stack frame so the context switcher can get to it */
_exception_stack_frame = ifr;
_Thread_Dispatch();
/* and make sure its clear in case we didn't dispatch. if we did, its
* already cleared */
_exception_stack_frame = NULL;
}
}
void __ISR_Handler(void)
{
register uint32_t level;
/* Interrupts are disabled upon entry to this Handler */
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
if ( _ISR_Nest_level == 0 ) {
/* Install irq stack */
_old_stack_ptr = stack_ptr;
stack_ptr = _CPU_Interrupt_stack_high - 4;
}
#endif
_ISR_Nest_level++;
_Thread_Dispatch_increment_disable_level();
__IIC_Handler();
/* Make sure that interrupts are disabled again */
_CPU_ISR_Disable( level );
_Thread_Dispatch_decrement_disable_level();
_ISR_Nest_level--;
if( _ISR_Nest_level == 0) {
#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
stack_ptr = _old_stack_ptr;
#endif
if( !_Thread_Dispatch_in_critical_section() )
{
if ( _Thread_Dispatch_necessary ) {
_CPU_ISR_Enable( level );
_Thread_Dispatch();
/* may have switched to another task and not return here immed. */
_CPU_ISR_Disable( level ); /* Keep _pairs_ of Enable/Disable */
}
}
}
_CPU_ISR_Enable( level );
}
void connect_rdbg_exception()
{
interrupt_gate_descriptor *currentIdtEntry;
unsigned limit;
unsigned level;
/*
* Connect the Exception used to debug
*/
i386_get_info_from_IDTR (¤tIdtEntry, &limit);
_CPU_ISR_Disable(level);
create_interrupt_gate_descriptor (¤tIdtEntry[50], rtems_exception_prologue_50);
_CPU_ISR_Enable(level);
old_currentExcHandler = _currentExcHandler;
_currentExcHandler = BreakPointExcHdl ;
}
rtems_device_driver m860_console_read(rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg)
{
rtems_libio_rw_args_t *rw_args;
char *buffer;
int maximum;
int count;
Buf_t *tmp_buf;
rtems_unsigned32 level;
/*
* Set up interrupts
* FIXME: DANGER: WARNING:
* CICR and SIMASK must be set in any module that uses
* the CPM. Currently those are console-generic.c and
* network.c. If the registers are not set the same
* in both places, strange things may happen.
* If they are only set in one place, then an application
* that used the other module won't work correctly.
* Put this comment in each module that sets these 2 registers
*/
m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3,
SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */
m860.simask |= M860_SIMASK_LVM1;
rw_args = (rtems_libio_rw_args_t *) arg;
buffer = rw_args->buffer;
maximum = rw_args->count;
count = 0;
while (count == 0) {
if (rxBufList[minor]->len) {
while ((count < maximum) &&
(rxBufList[minor]->pos < rxBufList[minor]->len)) {
buffer[count++] = rxBufList[minor]->buf[rxBufList[minor]->pos++];
}
_CPU_ISR_Disable(level);
if (rxBufList[minor]->pos == rxBufList[minor]->len) {
if (rxBufList[minor]->next) {
tmp_buf=rxBufList[minor]->next;
free ((void *) rxBufList[minor]->buf);
free ((void *) rxBufList[minor]);
rxBufList[minor]=tmp_buf;
}
else {
free(rxBufList[minor]->buf);
rxBufList[minor]->buf=0;
rxBufList[minor]->len=0;
rxBufList[minor]->pos=0;
}
}
_CPU_ISR_Enable(level);
}
else
if(rxBufList[minor]->next && !rxBufList[minor]->len) {
tmp_buf = rxBufList[minor];
rxBufList[minor] = rxBufList[minor]->next;
free(tmp_buf);
}
/* sleep(1);*/
}
rw_args->bytes_moved = count;
return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
}
