static void generic_or1k_clock_initialize(void)
{
uint64_t frequency = (1000000000 / OR1K_CLOCK_CYCLE_TIME_NANOSECONDS);
uint32_t TTMR;
/* For TTMR register,
* The least significant 28 bits are the number of clock cycles
* before generating a tick timer interrupt. While the most
* significant 4 bits are used for mode configuration, tick timer
* interrupt enable and pending interrupts status.
*/
/* FIXME: Long interval should pass since initializing the tick timer
* registers fires exceptions dispite interrupts has not been enabled yet.
*/
TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
(0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK)
) & ~(CPU_OR1K_SPR_TTMR_IP);
_OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
_OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
/* Initialize timecounter */
or1ksim_tc.tc_get_timecount = or1ksim_get_timecount;
or1ksim_tc.tc_counter_mask = 0xffffffff;
or1ksim_tc.tc_frequency = frequency;
or1ksim_tc.tc_quality = RTEMS_TIMECOUNTER_QUALITY_CLOCK_DRIVER;
rtems_timecounter_install(&or1ksim_tc);
}
static void generic_or1k_clock_cleanup(void)
{
uint32_t sr;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
/* Disable tick timer exceptions */
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)
& ~CPU_OR1K_SPR_SR_TEE);
/* Invalidate tick timer config registers */
_OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
_OR1K_mtspr(CPU_OR1K_SPR_TTMR, 0);
}
static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
_ISR_Enable(level);
}
static void generic_or1k_clock_at_tick(void)
{
uint32_t TTMR;
/* For TTMR register,
* The least significant 28 bits are the number of clock cycles
* before generating a tick timer interrupt. While the most
* significant 4 bits are used for mode configuration, tick timer
* interrupt enable and pending interrupts status.
*/
TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
(TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT & CPU_OR1K_SPR_TTMR_TP_MASK)
) & ~(CPU_OR1K_SPR_TTMR_IP);
_OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
_OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
cpu_counter_ticks += TTMR_NUM_OF_CLOCK_TICKS_INTERRUPT;
}
static inline void _CPU_OR1K_Cache_instruction_block_lock
(const void *d_addr)
{
ISR_Level level;
_ISR_Disable (level);
_OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
_ISR_Enable(level);
}
static inline void _CPU_OR1K_Cache_enable_data(void)
{
uint32_t sr;
ISR_Level level;
_ISR_Disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
_ISR_Enable(level);
}
static inline void _CPU_OR1K_Cache_disable_instruction(void)
{
uint32_t sr;
ISR_Level level;
_ISR_Disable (level);
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
_OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE));
_ISR_Enable(level);
}
static void generic_or1k_clock_initialize(void)
{
uint32_t TTMR;
/* For TTMR register,
* The least significant 28 bits are the number of clock cycles
* before generating a tick timer interrupt. While the most
* significant 4 bits are used for mode configuration, tick timer
* interrupt enable and pending interrupts status.
*/
/* FIXME: Long interval should pass since initializing the tick timer
* registers fires exceptions dispite interrupts has not been enabled yet.
*/
TTMR = (CPU_OR1K_SPR_TTMR_MODE_RESTART | CPU_OR1K_SPR_TTMR_IE |
(0xFFED9 & CPU_OR1K_SPR_TTMR_TP_MASK)
) & ~(CPU_OR1K_SPR_TTMR_IP);
_OR1K_mtspr(CPU_OR1K_SPR_TTMR, TTMR);
_OR1K_mtspr(CPU_OR1K_SPR_TTCR, 0);
/* Initialize CPU Counter */
cpu_counter_ticks = 0;
}
/**
* @brief Sets the hardware interrupt level by the level value.
*
* @param[in] level for or1k can only range over two values:
* 0 (enable interrupts) and 1 (disable interrupts). In future
* implementations if fast context switch is implemented, the level
* can range from 0 to 15. @see OpenRISC architecture manual.
*
*/
void _CPU_ISR_Set_level(uint32_t level)
{
uint32_t sr = 0;
level = (level > 0)? 1 : 0;
/* map level bit to or1k interrupt enable/disable bit in sr register */
level <<= CPU_OR1K_SPR_SR_SHAMT_IEE;
sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
if (level == 0){ /* Enable all interrupts */
sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
} else{
sr &= ~CPU_OR1K_SPR_SR_IEE;
}
_OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
}
