/**
* @brief This function writes data to the LCD
* @param Character data to be written on LCD
* @retval None
*/
void ASK25_LCD_Write_Data (uint8_t Character)
{
uint16_t Mask;
uint16_t LcdData = Character;
LcdData = LcdData << LCD_DATA_START_PIN;
Mask = (0x0F << (LCD_DATA_START_PIN));
ASK25_LCD_Write_Command(CURSOR_OFF); // Needed
#ifdef LCD_4BIT
{
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_SET); // Set RS
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Clear RW
HAL_GPIO_WritePin(GPIOE, _SBF(8, 0xF0), GPIO_PIN_RESET); // Clear Old Value
HAL_GPIO_WritePin(GPIOE, _SBF(8, ((LcdData >> 4) & Mask)), GPIO_PIN_SET);
ASK25_LCD_Enable();
HAL_GPIO_WritePin(GPIOE, _SBF(8, 0xF0), GPIO_PIN_RESET); // Clear Old Value
HAL_GPIO_WritePin(GPIOE, _SBF(8, (LcdData & Mask)), GPIO_PIN_SET);
ASK25_LCD_Enable();
}
#endif
#ifdef LCD_8BIT
{
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_SET); // Set RS
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Clear RW
HAL_GPIO_WritePin(GPIOE, _SBF(8,0xFF), GPIO_PIN_RESET); // Clear Old Value
HAL_GPIO_WritePin(GPIOE, _SBF(8,Character), GPIO_PIN_SET); // Send Data
ASK25_LCD_Enable();
}
#endif
}
/**
* @brief Configure Pins of LCD
* @retval None
*/
void ASK25_LCD_Config (void)
{
GPIO_InitTypeDef GPIO_InitStruct;
/* Enable the GPIO_ALED Clock */
__GPIOE_CLK_ENABLE();
__GPIOB_CLK_ENABLE();
#ifdef LCD_4BIT
{
GPIO_InitStruct.Pin = _SBF(8,0xF0);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
}
#endif
#ifdef LCD_8BIT
{
/* Configure the GPIO_ALED pin */
GPIO_InitStruct.Pin = _SBF(8,0xFF);
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
}
#endif
GPIO_InitStruct.Pin = 0x32;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
}
static void rk_ahash_reg_init(struct rk_crypto_info *dev)
{
int reg_status = 0;
reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL) |
RK_CRYPTO_HASH_FLUSH | _SBF(0xffff, 16);
CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, reg_status);
reg_status = CRYPTO_READ(dev, RK_CRYPTO_CTRL);
reg_status &= (~RK_CRYPTO_HASH_FLUSH);
reg_status |= _SBF(0xffff, 16);
CRYPTO_WRITE(dev, RK_CRYPTO_CTRL, reg_status);
memset_io(dev->reg + RK_CRYPTO_HASH_DOUT_0, 0, 32);
CRYPTO_WRITE(dev, RK_CRYPTO_INTENA, RK_CRYPTO_HRDMA_ERR_ENA |
RK_CRYPTO_HRDMA_DONE_ENA);
CRYPTO_WRITE(dev, RK_CRYPTO_INTSTS, RK_CRYPTO_HRDMA_ERR_INT |
RK_CRYPTO_HRDMA_DONE_INT);
CRYPTO_WRITE(dev, RK_CRYPTO_HASH_CTRL, dev->mode |
RK_CRYPTO_HASH_SWAP_DO);
CRYPTO_WRITE(dev, RK_CRYPTO_CONF, RK_CRYPTO_BYTESWAP_HRFIFO |
RK_CRYPTO_BYTESWAP_BRFIFO |
RK_CRYPTO_BYTESWAP_BTFIFO);
CRYPTO_WRITE(dev, RK_CRYPTO_HASH_MSG_LEN, dev->total);
}
/**
* @brief This function writes commands to the LCD
* @param Command command to be written on LCD
* @retval None
*/
void ASK25_LCD_Write_Command (uint8_t Command)
{
uint16_t Mask;
uint16_t LcdData = Command;
LcdData = LcdData << LCD_DATA_START_PIN;
Mask = (0x0F << (LCD_DATA_START_PIN));
#ifdef LCD_4BIT
{
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_RESET); // Clear RS
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Clear RW
HAL_GPIO_WritePin(GPIOE, _SBF(8, 0xF0), GPIO_PIN_RESET); // Clear Old Value
HAL_GPIO_WritePin(GPIOE, _SBF(8, ((LcdData >> 4) & Mask)), GPIO_PIN_SET);
ASK25_LCD_Enable();
HAL_GPIO_WritePin(GPIOE, _SBF(8, 0xF0), GPIO_PIN_RESET); // Clear Old Value
HAL_GPIO_WritePin(GPIOE, _SBF(8, (LcdData & Mask)), GPIO_PIN_SET);
ASK25_LCD_Enable();
}
#endif
#ifdef LCD_8BIT
{
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_1, GPIO_PIN_RESET); // Clear RS
HAL_GPIO_WritePin(GPIOB, GPIO_PIN_4, GPIO_PIN_RESET); // Clear RW
HAL_GPIO_WritePin(GPIOE, _SBF(8,0xFF), GPIO_PIN_RESET); // Clear Old Value
HAL_GPIO_WritePin(GPIOE, _SBF(8,Command), GPIO_PIN_SET); // Send Command
ASK25_LCD_Enable();
}
#endif
}
/*********************************************************************//**
* @brief Set value for CAS latency
* @param[in] index index number, should be from 0 to 3
* @param[in] ras_val CAS value should be in range: 0..3
* @return None
**********************************************************************/
void EMC_DynMemCAS(uint32_t index , uint32_t cas_val)
{
uint32_t mask = ~(uint32_t)(_SBF(8, 0x03)) ;
switch ( index)
{
case 0:
LPC_EMC->DynamicRasCas0 = (LPC_EMC->DynamicRasCas0 & mask) | cas_val;
break;
case 1:
LPC_EMC->DynamicRasCas1 = (LPC_EMC->DynamicRasCas1 & mask) | cas_val;
break;
case 2:
LPC_EMC->DynamicRasCas2 = (LPC_EMC->DynamicRasCas2 & mask )| cas_val;
break;
case 3:
LPC_EMC->DynamicRasCas3 = ( LPC_EMC->DynamicRasCas3 & mask) | cas_val;
break;
}
}
/*********************************************************************//**
* @brief Configure the memory device
* @param[in] index index number, should be from 0 to 3
* @param[in] mem_dev Memory device, should be:
* - 0x00: SDRAM
* - 0x01: Low-power SDRAM
* - 0x02: Micron Syncflash
* @return None
**********************************************************************/
void EMC_DynMemConfigMD(uint32_t index , uint32_t mem_dev)
{
uint32_t mask = ~(uint32_t)(_SBF(3, 0x03));
switch ( index)
{
case 0:
LPC_EMC->DynamicConfig0 = (LPC_EMC->DynamicConfig0 & mask) | mem_dev;
break;
case 1:
LPC_EMC->DynamicConfig1 = (LPC_EMC->DynamicConfig1 & mask) | mem_dev;
break;
case 2:
LPC_EMC->DynamicConfig2 =(LPC_EMC->DynamicConfig2 & mask) | mem_dev;
break;
case 3:
LPC_EMC->DynamicConfig3 = (LPC_EMC->DynamicConfig3 & mask) | mem_dev;
break;
}
}
/*********************************************************************//**
* @brief Map the address for the memory device
* @param[in] index index number, should be from 0 to 3
* @param[in] add_mapped address where the memory will be mapped
* @return None
**********************************************************************/
void EMC_DynMemConfigAM ( uint32_t index , uint32_t add_mapped )
{
uint32_t mask = ~ ( uint32_t ) ( _SBF ( 7, 0x3f ) ) | ~ ( uint32_t ) ( _BIT ( 14 ) ) ;
switch ( index )
{
case 0:
LPC_EMC->DynamicConfig0 = ( LPC_EMC->DynamicConfig0 & mask ) | add_mapped;
break;
case 1:
LPC_EMC->DynamicConfig1 = ( LPC_EMC->DynamicConfig1 & mask ) | add_mapped;
break;
case 2:
LPC_EMC->DynamicConfig2 = ( LPC_EMC->DynamicConfig2 & mask ) | add_mapped;
break;
case 3:
LPC_EMC->DynamicConfig3 = ( LPC_EMC->DynamicConfig3 & mask ) | add_mapped;
break;
}
}
/***********************************************************************
*
* Function: i2s_dma_init_dev
*
* Purpose: Initialize DMA for I2S
*
* Processing:
* See function
*
* Parameters:
* dmach: DMA Channel number
* p_i2s_dma_prms: dma parameters
*
*
* Outputs: None
*
* Returns: if ok returns TRUE
*
*
**********************************************************************/
INT_32 i2s_dma_init_dev(INT_32 devid, I2S_DMA_PRMS_T *p_i2s_dma_prms)
{
INT_32 DMAC_CHAN_DEST_WIDTH;
INT_32 DMAC_CHAN_SRC_WIDTH ;
INT_32 i2s_ww, i2sch;
INT_32 dmach, dir, mem, sz;
I2S_CFG_T *pi2s = (I2S_CFG_T *) devid;
i2sch = pi2s->i2snum;
i2s_ww = pi2s->i2s_w_sz ;
dmach = p_i2s_dma_prms->dmach;
dir = p_i2s_dma_prms->dir;
mem = p_i2s_dma_prms->mem;
sz = p_i2s_dma_prms->sz;
/* clear TC for the selected dma channel */
DMAC->int_tc_clear |= _SBF(0, dmach);
/* Set the DMA src and dst word width based on I2S Word
width setting */
if (i2s_ww == I2S_WW8)
{
DMAC_CHAN_DEST_WIDTH = DMAC_CHAN_DEST_WIDTH_8;
DMAC_CHAN_SRC_WIDTH = DMAC_CHAN_SRC_WIDTH_8;
}
else if (i2s_ww == I2S_WW16)
{
DMAC_CHAN_DEST_WIDTH = DMAC_CHAN_DEST_WIDTH_16;
DMAC_CHAN_SRC_WIDTH = DMAC_CHAN_SRC_WIDTH_16;
}
else
{
DMAC_CHAN_DEST_WIDTH = DMAC_CHAN_DEST_WIDTH_32;
DMAC_CHAN_SRC_WIDTH = DMAC_CHAN_SRC_WIDTH_32;
}
/* Setup DMA for I2S Channel 0, DEST uses AHB1, SRC uses AHB0 */
if (i2sch == I2S_CH0)
{
/* dma is flow controller */
if (dir == DMAC_CHAN_FLOW_D_M2P)
{
DMAC->dma_chan[dmach].src_addr = mem;
DMAC->dma_chan[dmach].dest_addr = (UNS_32) & I2S0->i2s_tx_fifo;
DMAC->dma_chan[dmach].control = DMAC_CHAN_TRANSFER_SIZE(sz)
| DMAC_CHAN_SRC_BURST_4
| DMAC_CHAN_DEST_BURST_4
| DMAC_CHAN_DEST_AHB1
| DMAC_CHAN_SRC_AUTOINC
| DMAC_CHAN_INT_TC_EN
| DMAC_CHAN_SRC_WIDTH
| DMAC_CHAN_DEST_WIDTH;
DMAC->dma_chan[dmach].config_ch |= DMAC_CHAN_ENABLE
| DMAC_DEST_PERIP(DMA_PERID_I2S0_DMA0)
| DMAC_CHAN_FLOW_D_M2P | DMAC_CHAN_IE
| DMAC_CHAN_ITC;
}
/* peripheral is flow controller */
else if (dir == DMAC_CHAN_FLOW_P_M2P)
{
DMAC->dma_chan[dmach].src_addr = mem;
DMAC->dma_chan[dmach].dest_addr = (UNS_32) & I2S0->i2s_tx_fifo;
DMAC->dma_chan[dmach].control = DMAC_CHAN_SRC_BURST_4
| DMAC_CHAN_DEST_BURST_4
| DMAC_CHAN_DEST_AHB1
| DMAC_CHAN_SRC_AUTOINC
| DMAC_CHAN_INT_TC_EN
| DMAC_CHAN_SRC_WIDTH
| DMAC_CHAN_DEST_WIDTH;
DMAC->dma_chan[dmach].config_ch |= DMAC_CHAN_ENABLE
| DMAC_DEST_PERIP(DMA_PERID_I2S0_DMA0)
| DMAC_CHAN_FLOW_P_M2P | DMAC_CHAN_IE
| DMAC_CHAN_ITC;
}
/* dma is flow controller */
else if (dir == DMAC_CHAN_FLOW_D_P2M)
{
DMAC->dma_chan[dmach].src_addr = (UNS_32) & I2S0->i2s_rx_fifo;
DMAC->dma_chan[dmach].dest_addr = mem;
DMAC->dma_chan[dmach].control = DMAC_CHAN_TRANSFER_SIZE(sz)
| DMAC_CHAN_SRC_BURST_4
| DMAC_CHAN_DEST_BURST_4
| DMAC_CHAN_SRC_AHB1
| DMAC_CHAN_DEST_AUTOINC
| DMAC_CHAN_INT_TC_EN
| DMAC_CHAN_SRC_WIDTH
| DMAC_CHAN_DEST_WIDTH;
DMAC->dma_chan[dmach].config_ch |= DMAC_CHAN_ENABLE
| DMAC_SRC_PERIP(DMA_PERID_I2S0_DMA1)
| DMAC_CHAN_FLOW_D_P2M | DMAC_CHAN_IE
| DMAC_CHAN_ITC;
}
/* peripheral is flow controller */
else if (dir == DMAC_CHAN_FLOW_P_P2M)
{
DMAC->dma_chan[dmach].src_addr = (UNS_32) & I2S0->i2s_rx_fifo;
DMAC->dma_chan[dmach].dest_addr = mem;
DMAC->dma_chan[dmach].control = DMAC_CHAN_SRC_BURST_4
| DMAC_CHAN_DEST_BURST_4
| DMAC_CHAN_SRC_AHB1
| DMAC_CHAN_DEST_AUTOINC
| DMAC_CHAN_INT_TC_EN
| DMAC_CHAN_SRC_WIDTH
| DMAC_CHAN_DEST_WIDTH;
DMAC->dma_chan[dmach].config_ch |= DMAC_CHAN_ENABLE
| DMAC_SRC_PERIP(DMA_PERID_I2S0_DMA1)
| DMAC_CHAN_FLOW_P_P2M | DMAC_CHAN_IE
| DMAC_CHAN_ITC;
}
}
/* Setup DMA for I2S Channel 1 */
else if (i2sch == I2S_CH1)
{
/* dma is flow controller */
if (dir == DMAC_CHAN_FLOW_D_M2P)
{
DMAC->dma_chan[dmach].src_addr = mem;
DMAC->dma_chan[dmach].dest_addr = (UNS_32) & I2S1->i2s_tx_fifo;
DMAC->dma_chan[dmach].control = DMAC_CHAN_TRANSFER_SIZE(sz)
| DMAC_CHAN_SRC_BURST_4
| DMAC_CHAN_DEST_BURST_4
| DMAC_CHAN_DEST_AHB1
| DMAC_CHAN_SRC_AUTOINC
| DMAC_CHAN_INT_TC_EN
| DMAC_CHAN_SRC_WIDTH
| DMAC_CHAN_DEST_WIDTH;
DMAC->dma_chan[dmach].config_ch |= DMAC_CHAN_ENABLE
| DMAC_DEST_PERIP(DMA_PERID_I2S1_DMA0)
| DMAC_CHAN_FLOW_D_M2P | DMAC_CHAN_IE
| DMAC_CHAN_ITC;
}
/* peripheral is flow controller */
else if (dir == DMAC_CHAN_FLOW_P_M2P)
{
DMAC->dma_chan[dmach].src_addr = mem;
DMAC->dma_chan[dmach].dest_addr = (UNS_32) & I2S1->i2s_tx_fifo;
DMAC->dma_chan[dmach].control = DMAC_CHAN_SRC_BURST_4
| DMAC_CHAN_DEST_BURST_4
| DMAC_CHAN_DEST_AHB1
| DMAC_CHAN_SRC_AUTOINC
| DMAC_CHAN_INT_TC_EN
| DMAC_CHAN_SRC_WIDTH
| DMAC_CHAN_DEST_WIDTH;
DMAC->dma_chan[dmach].config_ch |= DMAC_CHAN_ENABLE
| DMAC_DEST_PERIP(DMA_PERID_I2S1_DMA0)
| DMAC_CHAN_FLOW_P_M2P | DMAC_CHAN_IE
| DMAC_CHAN_ITC;
}
/* dma is flow controller */
else if (dir == DMAC_CHAN_FLOW_D_P2M)
{
DMAC->dma_chan[dmach].src_addr = (UNS_32) & I2S1->i2s_rx_fifo;
DMAC->dma_chan[dmach].dest_addr = mem;
DMAC->dma_chan[dmach].control = DMAC_CHAN_TRANSFER_SIZE(sz)
| DMAC_CHAN_SRC_BURST_4
| DMAC_CHAN_DEST_BURST_4
| DMAC_CHAN_SRC_AHB1
| DMAC_CHAN_DEST_AUTOINC
| DMAC_CHAN_INT_TC_EN
| DMAC_CHAN_SRC_WIDTH
| DMAC_CHAN_DEST_WIDTH;
DMAC->dma_chan[dmach].config_ch |= DMAC_CHAN_ENABLE
| DMAC_SRC_PERIP(DMA_PERID_I2S1_DMA1)
| DMAC_CHAN_FLOW_D_P2M
| DMAC_CHAN_IE
| DMAC_CHAN_ITC;
}
/* peripheral is flow controller */
else if (dir == DMAC_CHAN_FLOW_P_P2M)
{
DMAC->dma_chan[dmach].src_addr = (UNS_32) & I2S1->i2s_rx_fifo;
DMAC->dma_chan[dmach].dest_addr = mem;
DMAC->dma_chan[dmach].control = DMAC_CHAN_SRC_BURST_4
| DMAC_CHAN_DEST_BURST_4
| DMAC_CHAN_SRC_AHB1
| DMAC_CHAN_DEST_AUTOINC
| DMAC_CHAN_INT_TC_EN
| DMAC_CHAN_SRC_WIDTH
| DMAC_CHAN_DEST_WIDTH;
DMAC->dma_chan[dmach].config_ch |= DMAC_CHAN_ENABLE
| DMAC_SRC_PERIP(DMA_PERID_I2S1_DMA1)
| DMAC_CHAN_FLOW_P_P2M
| DMAC_CHAN_IE
| DMAC_CHAN_ITC;
}
}
else
{
return (FALSE);
}
return(TRUE);
}
/*********************************************************************//**
* @brief Issue SDRAM command
* @param[in] SDRAM_command Command mode, should be:
* - 0x00: Issue SDRAM NORMAL operation command
* - 0x01: Issue SDRAM MODE command
* - 0x02: Issue SDRAM PALL (precharge all) command
* - 0x03: Issue SRAM NOP (no operation) command
* @return None
**********************************************************************/
void EMC_DynCtrlSDRAMInit ( uint32_t SDRAM_command )
{
uint32_t mask = ~ ( uint32_t ) ( _SBF ( 7, 0x03 ) );
LPC_EMC->DynamicControl = ( ( LPC_EMC->DynamicControl & mask ) | SDRAM_command );
}
