/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_sam3_init(struct device *arg)
{
uint32_t key;
ARG_UNUSED(arg);
/* Note:
* Magic numbers below are obtained by reading the registers
* when the SoC was running the SAM-BA bootloader
* (with reserved bits set to 0).
*/
key = irq_lock();
/* Setup the vector table offset register (VTOR),
* which is located at the beginning of flash area.
*/
_scs_relocate_vector_table((void *)CONFIG_FLASH_BASE_ADDRESS);
/* Setup the flash controller.
* The bootloader is running @ 48 MHz with
* FWS == 2.
* When running at 84 MHz, FWS == 4 seems
* to be more stable, and allows the board
* to boot.
*/
__EEFC0->fmr = 0x00000400;
__EEFC1->fmr = 0x00000400;
/* Clear all faults */
_ScbMemFaultAllFaultsReset();
_ScbBusFaultAllFaultsReset();
_ScbUsageFaultAllFaultsReset();
_ScbHardFaultAllFaultsReset();
/* Setup master clock */
clock_init();
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
return 0;
}
static int fsl_frdm_k64f_init(struct device *arg)
{
ARG_UNUSED(arg);
/* System Integration module */
volatile struct K20_SIM *sim_p =
(volatile struct K20_SIM *)PERIPH_ADDR_BASE_SIM;
/* Power Mgt Control module */
volatile struct K6x_PMC *pmc_p =
(volatile struct K6x_PMC *)PERIPH_ADDR_BASE_PMC;
/* Power Mgt Control module */
volatile struct K6x_MPU *mpu_p =
(volatile struct K6x_MPU *)PERIPH_ADDR_BASE_MPU;
int oldLevel; /* old interrupt lock level */
uint32_t temp_reg;
/* disable interrupts */
oldLevel = irq_lock();
/* enable the port clocks */
sim_p->scgc5.value |= (SIM_SCGC5_PORTA_CLK_EN | SIM_SCGC5_PORTB_CLK_EN |
SIM_SCGC5_PORTC_CLK_EN | SIM_SCGC5_PORTD_CLK_EN |
SIM_SCGC5_PORTE_CLK_EN);
/* release I/O power hold to allow normal run state */
pmc_p->regsc.value |= PMC_REGSC_ACKISO_MASK;
/*
* Disable memory protection and clear slave port errors.
* Note that the K64F does not implement the optional ARMv7-M memory
* protection unit (MPU), specified by the architecture (PMSAv7), in the
* Cortex-M4 core. Instead, the processor includes its own MPU module.
*/
temp_reg = mpu_p->ctrlErrStatus.value;
temp_reg &= ~MPU_VALID_MASK;
temp_reg |= MPU_SLV_PORT_ERR_MASK;
mpu_p->ctrlErrStatus.value = temp_reg;
/* clear all faults */
_ScbMemFaultAllFaultsReset();
_ScbBusFaultAllFaultsReset();
_ScbUsageFaultAllFaultsReset();
_ScbHardFaultAllFaultsReset();
/*
* Initialize the clock dividers for:
* core and system clocks = 120 MHz (PLL/OUTDIV1)
* bus clock = 60 MHz (PLL/OUTDIV2)
* FlexBus clock = 40 MHz (PLL/OUTDIV3)
* Flash clock = 24 MHz (PLL/OUTDIV4)
*/
sim_p->clkdiv1.value = (
(SIM_CLKDIV(CONFIG_K64_CORE_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV1_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_BUS_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV2_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_FLEXBUS_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV3_SHIFT) |
(SIM_CLKDIV(CONFIG_K64_FLASH_CLOCK_DIVIDER) <<
SIM_CLKDIV1_OUTDIV4_SHIFT));
/* Initialize PLL/system clock to 120 MHz */
clkInit();
/*
* install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
/* restore interrupt state */
irq_unlock(oldLevel);
return 0;
}
