/*******************************************************************************
* Function Name : HardFault_Handler
* Description : This function handles Hard Fault exception.
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void HardFault_Handler(void)
{
unsigned int contr_reg;
contr_reg = __get_CONTROL();
if(contr_reg&2)
{
#if defined ( __CMCARM__ )
__ASM MRS R0, PSP;
#else
__ASM("MRS R0, PSP");
#endif
}
else{
#if defined ( __CMCARM__ )
__ASM MRS R0, MSP;
#else
__ASM("MRS R0, MSP");
#endif
}
//top of stack is in R0. It is passed to C-function.
#if defined ( __CMCARM__ )
__ASM BL (Hard_fault_handler_c);
#else
__ASM("BL (Hard_fault_handler_c)");
#endif
/* Go to infinite loop when Hard Fault exception occurs */
while (1);
}
void show() {
noInterrupts();
for (int i = 0; i < number_of_LEDs; i++) {
for (int j = 7; j >= 0; j--) {
NRF_GPIO->OUTSET = (1UL << LED);
if (led_GRB_array[i] & (0x01 << j)) {
__ASM ( \
" NOP\n\t" \
" NOP\n\t" \
" NOP\n\t" \
" NOP\n\t" \
" NOP\n\t" \
);
NRF_GPIO->OUTCLR = (1UL << LED);
}
else {
NRF_GPIO->OUTCLR = (1UL << LED);
__ASM ( \
" NOP\n\t" \
" NOP\n\t" \
" NOP\n\t" \
);
}
}
}
delayMicroseconds(50); // latch and reset WS2812.
interrupts();
}
int __rt_ffs(int value)
{
if (value == 0) return value;
__ASM("RBIT r0, r0");
__ASM("CLZ r0, r0");
__ASM("ADDS r0, r0, #0x01");
}
void __attribute__((interrupt("IRQ"))) HardFault_Handler(void)
{
__ASM("TST LR, #4");
__ASM("ITE EQ");
__ASM("MRSEQ R0, MSP");
__ASM("MRSNE R0, PSP");
__ASM("B hard_fault_handler");
}
/*
*
* === FUNCTION ======================================================================
* Name: stim_delay
* Description: wait some milliseconds.It will blocking process until time out.
* =====================================================================================
*/
void stim_delay ( uint16_t delayms)
{
struct stim_event *event;
__ASM("CPSID I");
event = push_event(delayms,NULL,1);
__ASM("CPSIE I");
while(event->now < event->interval);
} /* ----- end of function stim_delay ----- */
void _delay_ms(unsigned delayTicks){
delayTicks *=(uint64_t)SystemCoreClock/10000u;
while(delayTicks--)
{
__ASM("nop");
}
}
// estimate the bandgap voltage in terms of Vcc ladder steps, returns as mV
int acmpVccEstimate () {
LPC_SYSCON->PDRUNCFG &= ~(1<<15); // power up comparator
LPC_SYSCON->SYSAHBCLKCTRL |= (1<<19); // ACMP & IOCON clocks
//LPC_SYSCON->PRESETCTRL &= ~(1<<12); // reset comparator
//LPC_SYSCON->PRESETCTRL |= (1<<12); // release comparator
// connect ladder to CMP+ and bandgap to CMP-
LPC_CMP->CTRL = (6<<11); // careful: 6 on LPC81x, 5 on LPC82x !
int i, n;
for (i = 2; i < 32; ++i) {
LPC_CMP->LAD = (i << 1) | 1; // use ladder tap i
for (n = 0; n < 100; ++n) __ASM(""); // brief settling delay
if (LPC_CMP->CTRL & (1<<21)) // if COMPSTAT bit is set
break; // ... we're done
}
// the result is the number of Vcc/31 ladder taps, i.e.
// tap * (Vcc / 31) = 0.9
// therefore:
// Vcc = (0.9 * 31) / tap
// or, in millivolt:
int tap = i - 1;
return (900 * 31) / tap;
LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<19); // ACMP & IOCON clocks
LPC_SYSCON->PDRUNCFG |= (1<<15);
}
//! @brief Usage Fault Handler
void UsageFault_Handler(void)
{
#if defined (DEBUG)
__ASM("BKPT #0");
#endif // DEBUG
// Reset MCU
NVIC_SystemReset();
}
void delay(void)
{
volatile uint32_t delayTicks = 2000000;
while (delayTicks--)
{
__ASM("nop");
}
}
/**
* \brief Sync Sleep for several ms
*/
extern void Sleep( volatile uint32_t dwMs )
{
uint32_t dwStart ;
uint32_t dwCurrent ;
__ASM("CPSIE I");
dwStart = _dwTickCount ;
do
{
dwCurrent = _dwTickCount ;
if ( dwCurrent - dwStart > dwMs )
{
break ;
}
__ASM("WFI");
} while( 1 ) ;
}
// measure the voltage on PIO0_1, returns a value from 0 to 32
// the steps will be roughly 0.1V apart, from 0 to 3.3V
int analogMeasure () {
int i;
for (i = 0; i < 32; ++i) {
LPC_CMP->LAD = (i << 1) | 1; // use ladder tap i
for (int i = 0; i < 100; ++i) __ASM(""); // brief settling delay
if (LPC_CMP->CTRL & (1<<21)) // if COMPSTAT bit is set
break; // ... we're done
}
return i;
}
/*****************************************************************************
Prototype : USART1_IRQHandler
Description : uart1 interrupt hander
Input : void
Output : None
Return Value :
Calls :
Called By :
History :
1.Date : 2015/9/2
Author : qiuweibo
Modification : Created function
*****************************************************************************/
void USART1_IRQHandler(void)
{
volatile char temp = 0;
BaseType_t xHigherPriorityTaskWoken, xResult;
// We have not woken a task at the start of the ISR.
xHigherPriorityTaskWoken = pdFALSE;
if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET)
{
temp = USART_ReceiveData(USART1);
xResult = xQueueSendToBackFromISR(uart1_rx_queue, (void *)&temp, &xHigherPriorityTaskWoken);
if (errQUEUE_FULL == xResult)
{
//TODO: do something.
__ASM("nop;");
}
if(USART_GetFlagStatus(USART1, USART_FLAG_ORE) != RESET)
{
USART_ClearFlag(USART1, USART_FLAG_ORE);
USART_ReceiveData(USART1);
}
}
if(USART_GetITStatus(USART1, USART_IT_TXE) != RESET)
{
xResult = xQueueReceiveFromISR(uart1_tx_queue, (void *)&temp, &xHigherPriorityTaskWoken);
if (pdPASS == xResult)
{
USART_SendData(USART1, temp);
}
else //empty
{
USART_ITConfig(USART1, USART_IT_TXE, DISABLE);
}
}
// error happen
if(USART_GetITStatus(USART1, USART_IT_PE) != RESET)
{
USART_ClearITPendingBit(USART1, USART_IT_PE);
// udprintf("\r\n===============Uart1.Parity error");
}
if(USART_GetITStatus(USART1, USART_IT_FE | USART_IT_NE) != RESET)
{
USART_ClearITPendingBit(USART1, USART_IT_FE | USART_IT_NE);
}
if(xHigherPriorityTaskWoken)
{
taskYIELD ();
}
}
/**
* @brief 进入低功耗模式
* @param[in] enSleepOnExit 在系统唤醒时候 是否继续进入低功耗
* @retval None
* @note 任何中断 都可以唤醒CPU
*/
void EnterSTOPMode(bool enSleepOnExit)
{
/* unlock all VLP mode */
SMC->PMPROT |= 0xFF;
/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
(enSleepOnExit)?(SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk):(SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk);
/* WFI instruction will start entry into STOP mode */
__ASM("WFI");
}
/**
* @brief �������ģʽ
* @param enSleepOnExit:��ϵͳ����ʱ�� �Ƿ�����������
* @retval 0: �ɹ� ��0: ����
* @note �κ��ж� �����Ի���CPU
*/
void EnterSTOPMode(bool enSleepOnExit)
{
/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
if (enSleepOnExit)
{
SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
}
else
{
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
}
/* WFI instruction will start entry into STOP mode */
__ASM("WFI");
}
/**********************************************************************
name :
function :
**********************************************************************/
void delayMicroseconds( uint32_t us )
{
while (us--)
{
__ASM(" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t"
" NOP\n\t");
};
}
status_t PHY_AutoNegotiation(ENET_Type *base, uint32_t phyAddr)
{
status_t result = kStatus_Success;
uint32_t bssReg;
uint32_t counter = PHY_TIMEOUT_COUNT;
uint32_t timeDelay;
uint32_t ctlReg = 0;
/* Set the negotiation. */
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success)
{
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
if (result == kStatus_Success)
{
/* Check auto negotiation complete. */
while (counter --)
{
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
if ( result == kStatus_Success)
{
PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK))
{
/* Wait a moment for Phy status stable. */
for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
{
__ASM("nop");
}
break;
}
}
if (!counter)
{
return kStatus_PHY_AutoNegotiateFail;
}
}
}
}
return result;
}
/*FUNCTION**********************************************************************
*
* Function Name : QSPI_HAL_Deinit
* Description : Deinit QSPI. This function will disable QSPI clock.
*
*END**************************************************************************/
void QSPI_HAL_SoftwareReset(QuadSPI_Type * base)
{
/* Reset QSPI AHB domain */
QuadSPI_BWR_MCR_SWRSTHD(base,1U);
/* Reset QSPI buffer */
QuadSPI_BWR_MCR_SWRSTSD(base,1U);
/* Wait several ticks until the ahb domain and serial flash domain are reset*/
for (volatile uint32_t i=0; i<100; i++)
{
__ASM("nop");
}
/*Disable QSPI clock*/
QuadSPI_BWR_MCR_MDIS(base, 1U);
/* Clear the reset flag */
QuadSPI_BWR_MCR_SWRSTSD(base,0U);
QuadSPI_BWR_MCR_SWRSTHD(base,0U);
QuadSPI_BWR_MCR_MDIS(base, 0U);
}
/*******************************************************************************
* Code
******************************************************************************/
static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t regAddr)
{
uint16_t mask = L2CACHE_8WAYS_MASK;
uint32_t timeout = L2CACHE_OPERATION_TIMEOUT;
/* Check the ways used at first. */
if (auxCtlReg & L2CACHEC_REG1_AUX_CONTROL_ASSOCIATIVITY_MASK)
{
mask = L2CACHE_16WAYS_MASK;
}
/* Set the opeartion for all ways/entries of the cache. */
*(uint32_t *)regAddr = mask;
/* Waiting for until the operation is complete. */
while ((*(volatile uint32_t *)regAddr & mask) && timeout)
{
__ASM("nop");
timeout--;
}
}
/**
* @brief Return the Process Stack Pointer
*
* @param none
* @return uint32_t ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP (void)
{
__ASM ("mrs r0, psp");
__ASM ("bx lr");
}
static __INLINE void __SVC() { __ASM ("svc 0x01");}
void HASH_RNG_IRQHandler(void) {__ASM("bkpt 0");}
/**
* @brief Return the Main Stack Pointer
*
* @param none
* @return uint32_t Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP (void)
{
__ASM ("mrs r0, msp");
__ASM ("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param uint32_t Process Stack Pointer
* @return none
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP (uint32_t topOfProcStack)
{
__ASM ("msr psp, r0");
__ASM ("bx lr");
}
/**
* @brief LDR Exclusive
*
* @param uint32_t* address
* @return uint32_t value of (*address)
*
* Exclusive LDR command
*/
uint32_t __LDREXW (uint32_t * addr)
{
__ASM ("ldrex r0, [r0]");
__ASM ("bx lr");
}
/**
* @brief STR Exclusive
*
* @param uint32_t *address
* @param uint32_t value to store
* @return uint32_t successful / failed
*
* Exclusive STR command
*/
uint32_t __STREXW (uint32_t value, uint32_t * addr)
{
__ASM ("strex r0, r0, [r1]");
__ASM ("bx lr");
}
/**
* @brief LDR Exclusive
*
* @param uint16_t* address
* @return uint16_t value of (*address)
*
* Exclusive LDR command
*/
uint16_t __LDREXH (uint16_t * addr)
{
__ASM ("ldrexh r0, [r0]");
__ASM ("bx lr");
}
/**
* @brief LDR Exclusive
*
* @param uint8_t* address
* @return uint8_t value of (*address)
*
* Exclusive LDR command
*/
uint8_t __LDREXB (uint8_t * addr)
{
__ASM ("ldrexb r0, [r0]");
__ASM ("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param uint32_t value to reverse
* @return uint32_t reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT (uint32_t value)
{
__ASM ("rbit r0, r0");
__ASM ("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param uint16_t value to reverse
* @return uint32_t reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16 (uint16_t value)
{
__ASM ("rev16 r0, r0");
__ASM ("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param uint32_t Main Stack Pointer
* @return none
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP (uint32_t topOfMainStack)
{
__ASM ("msr msp, r0");
__ASM ("bx lr");
}
