/** * @brief Aborts the DMA Transfer in Interrupt mode. * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) { HAL_StatusTypeDef status = HAL_OK; if(HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; status = HAL_ERROR; } else { /* Disable DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); /* Disable the channel */ __HAL_DMA_DISABLE(hdma); /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Call User Abort callback */ if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); } } return status; }
/** * @brief DeInitialize the DMA peripheral. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA handle allocation */ if(hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); /* Check the DMA peripheral state */ if(hdma->State == HAL_DMA_STATE_BUSY) { return HAL_ERROR; } /* Disable the selected DMA Channelx */ __HAL_DMA_DISABLE(hdma); /* Reset DMA Channel control register */ hdma->Instance->CCR = 0; /* Reset DMA Channel Number of Data to Transfer register */ hdma->Instance->CNDTR = 0; /* Reset DMA Channel peripheral address register */ hdma->Instance->CPAR = 0; /* Reset DMA Channel memory address register */ hdma->Instance->CMAR = 0; /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Reset DMA channel selection register */ if (hdma->Instance == DMA1_Channel1) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S; } else if (hdma->Instance == DMA1_Channel2) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S; } else if (hdma->Instance == DMA1_Channel3) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S; } else if (hdma->Instance == DMA1_Channel4) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S; } else if (hdma->Instance == DMA1_Channel5) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S; } else if (hdma->Instance == DMA1_Channel6) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S; } else if (hdma->Instance == DMA1_Channel7) { /*Reset DMA request*/ DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S; } else if (hdma->Instance == DMA2_Channel1) { /*Reset DMA request*/ DMA2_CSELR->CSELR &= ~DMA_CSELR_C1S; } else if (hdma->Instance == DMA2_Channel2) { /*Reset DMA request*/ DMA2_CSELR->CSELR &= ~DMA_CSELR_C2S; } else if (hdma->Instance == DMA2_Channel3) { /*Reset DMA request*/ DMA2_CSELR->CSELR &= ~DMA_CSELR_C3S; } else if (hdma->Instance == DMA2_Channel4) { /*Reset DMA request*/ DMA2_CSELR->CSELR &= ~DMA_CSELR_C4S; } else if (hdma->Instance == DMA2_Channel5) { /*Reset DMA request*/ DMA2_CSELR->CSELR &= ~DMA_CSELR_C5S; } else if (hdma->Instance == DMA2_Channel6) { /*Reset DMA request*/ DMA2_CSELR->CSELR &= ~DMA_CSELR_C6S; } else if (hdma->Instance == DMA2_Channel7) { /*Reset DMA request*/ DMA2_CSELR->CSELR &= ~DMA_CSELR_C7S; } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hdma); return HAL_OK; }