void IRQportableStartKernel()
{
//Enable fault handlers
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA | SCB_SHCSR_BUSFAULTENA
| SCB_SHCSR_MEMFAULTENA;
//Enable traps for unaligned memory access and division by zero
SCB->CCR |= SCB_CCR_DIV_0_TRP | SCB_CCR_UNALIGN_TRP;
NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting
NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15)
NVIC_SetPriority(SysTick_IRQn,3);//High priority for SysTick (Max=0, min=15)
SysTick->LOAD=SystemCoreClock/miosix::TICK_FREQ;
//Start SysTick, set to generate interrupts
SysTick->CTRL=SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT |
SysTick_CTRL_CLKSOURCE;
#ifdef SCHED_TYPE_CONTROL_BASED
AuxiliaryTimer::IRQinit();
#endif //SCHED_TYPE_CONTROL_BASED
//create a temporary space to save current registers. This data is useless
//since there's no way to stop the sheduler, but we need to save it anyway.
unsigned int s_ctxsave[miosix::CTXSAVE_SIZE];
ctxsave=s_ctxsave;//make global ctxsave point to it
//Note, we can't use enableInterrupts() now since the call is not mathced
//by a call to disableInterrupts()
__enable_fault_irq();
__enable_irq();
miosix::Thread::yield();
//Never reaches here
}
/**
\brief Test case: TC_CoreFunc_FAULTMASK
\details
- Check if __get_FAULTMASK and __set_FAULTMASK intrinsic can be used to manipulate FAULTMASK.
- Check if __enable_fault_irq and __disable_fault_irq are reflected in FAULTMASK.
*/
void TC_CoreFunc_FAULTMASK (void) {
uint32_t orig = __get_FAULTMASK();
// toggle faultmask
uint32_t faultmask = (orig & ~0x01U) | (~orig & 0x01U);
__set_FAULTMASK(faultmask);
uint32_t result = __get_FAULTMASK();
ASSERT_TRUE(result == faultmask);
__disable_fault_irq();
result = __get_FAULTMASK();
ASSERT_TRUE((result & 0x01U) == 1U);
__enable_fault_irq();
result = __get_FAULTMASK();
ASSERT_TRUE((result & 0x01U) == 0U);
__disable_fault_irq();
result = __get_FAULTMASK();
ASSERT_TRUE((result & 0x01U) == 1U);
__set_FAULTMASK(orig);
}
/**
* Initializes the minimal system including CPU Clock, UART, and Flash accelerator
* Be careful of the order of the operations!!!
*/
void low_level_init(void)
{
rtc_init();
g_rtc_boot_time = rtc_gettime();
/* Configure System Clock based on desired clock rate @ sys_config.h */
sys_clock_configure();
configure_flash_acceleration(sys_get_cpu_clock());
/* Setup default interrupt priorities that will work with FreeRTOS */
configure_interrupt_priorities();
/* These methods shouldn't be needed but doing it anyway to be safe */
NVIC_SetPriorityGrouping(0);
__set_BASEPRI(0);
__enable_fault_irq();
__enable_irq();
/* Setup UART with minimal I/O functions */
uart0_init(SYS_CFG_UART0_BPS);
sys_set_outchar_func(uart0_putchar);
sys_set_inchar_func(uart0_getchar);
/**
* Turn off I/O buffering otherwise sometimes printf/scanf doesn't behave
* correctly due to strange buffering and/or flushing effects.
*/
setvbuf(stdout, 0, _IONBF, 0);
setvbuf(stdin, 0, _IONBF, 0);
/* Initialize newlib fopen() fread() calls support */
syscalls_init();
/* Enable the watchdog to allow us to recover in an event of system crash */
sys_watchdog_enable();
/* Uart and printf() are initialized, so print our boot-up message */
print_boot_info();
}
// I2C status flag initialization
void i2cInit() {
GPIO_InitTypeDef gs;
I2C_InitTypeDef is;
// Clocks on
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C1, ENABLE);
// GPIOs set up
gs.GPIO_Mode = GPIO_Mode_AF;
gs.GPIO_OType = GPIO_OType_OD;
gs.GPIO_PuPd = GPIO_PuPd_NOPULL;
gs.GPIO_Speed = GPIO_Speed_50MHz;
gs.GPIO_Pin = GPIO_Pin_6 | GPIO_Pin_9;
GPIO_Init(GPIOB, &gs);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource6, GPIO_AF_I2C1);
GPIO_PinAFConfig(GPIOB, GPIO_PinSource9, GPIO_AF_I2C1);
// Reset I2C
I2C1->CR1 = I2C_CR1_SWRST;
for (uint32_t delay = 0; delay < 128; delay++) asm volatile("");
I2C1->CR1 = 0;
// Configure I2C
is.I2C_ClockSpeed = 400000;
is.I2C_Mode = I2C_Mode_I2C;
is.I2C_DutyCycle = I2C_DutyCycle_2;
is.I2C_OwnAddress1 = 0x10;
is.I2C_Ack = I2C_Ack_Disable;
is.I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
I2C_Init(I2C1, &is);
I2C_Cmd(I2C1, ENABLE);
I2C1->CR2 |= I2C_CR2_ITERREN;
i2cState.status = 0;
// IRQs on
NVIC_EnableIRQ(I2C1_ER_IRQn);
NVIC_EnableIRQ(I2C1_EV_IRQn);
NVIC_SetPriority(I2C1_ER_IRQn, 1);
NVIC_SetPriority(I2C1_EV_IRQn, 1);
__enable_fault_irq();
__enable_irq();
}
void IRQportableStartKernel()
{
//Enable fault handlers
SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk
| SCB_SHCSR_MEMFAULTENA_Msk;
//Enable traps for division by zero. Trap for unaligned memory access
//was removed as gcc starting from 4.7.2 generates unaligned accesses by
//default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html)
SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk;
NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting
NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15)
NVIC_SetPriority(SysTick_IRQn,3);//High priority for SysTick (Max=0, min=15)
NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15)
SysTick->LOAD=SystemCoreClock/miosix::TICK_FREQ;
//Start SysTick, set to generate interrupts
SysTick->CTRL=SysTick_CTRL_ENABLE_Msk | SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_CLKSOURCE_Msk;
#ifdef WITH_PROCESSES
//Enable MPU
MPU->CTRL=MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk;
#endif //WITH_PROCESSES
#ifdef SCHED_TYPE_CONTROL_BASED
AuxiliaryTimer::IRQinit();
#endif //SCHED_TYPE_CONTROL_BASED
//create a temporary space to save current registers. This data is useless
//since there's no way to stop the sheduler, but we need to save it anyway.
unsigned int s_ctxsave[miosix::CTXSAVE_SIZE];
ctxsave=s_ctxsave;//make global ctxsave point to it
//Note, we can't use enableInterrupts() now since the call is not mathced
//by a call to disableInterrupts()
__enable_fault_irq();
__enable_irq();
miosix::Thread::yield();
//Never reaches here
}
