__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
//Vector 2 - RXIFG
case 2:
_wasReceived = 1;
__bic_SR_register_on_exit(LPM0_bits);
break;
default:
break;
}
}
__interrupt void Timer_A0(void) {
switch (__even_in_range(TA0IV, 10)) {
case 2:
//LPM3_EXIT;
break;
case 4:
EPD_Counter++;
LPM3_EXIT;
break;
}
}
__interrupt void USCI_A1_ISR(void)
{
switch(__even_in_range(UCA1IV, USCI_UART_UCTXCPTIFG))
{
case USCI_NONE: break;
case USCI_UART_UCRXIFG:
uart_a1_rx_int_handle(UCA1RXBUF);
break;
case USCI_UART_UCTXIFG: break;
case USCI_UART_UCSTTIFG: break;
case USCI_UART_UCTXCPTIFG: break;
}
}
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = UCA0RXBUF; // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
__interrupt void SNI_ISR (void)
{
switch (__even_in_range(SYSSNIV, 10)) // Efficient switch-implementation
{
case 2: break; // Vector 2: SVMIFG
case 4: P1OUT ^= BIT0; // Vector 4: VMAIFG
__bic_SR_register_on_exit(LPM0_bits); // Exit Active
break;
case 6: break; // Vector 6: JMBINIFG
case 8: break; // Vector 8: JMBOUTIFG
case 10: break; // Vector 10: Reserved
}
}
void ADC12ISR(void)
{
static uint16_t index = 0;
switch(__even_in_range(ADC12IV,34))
{
case 0: break; //Vector 0: No interrupt
case 2: break; //Vector 2: ADC overflow
case 4: break; //Vector 4: ADC timing overflow
case 6: break; //Vector 6: ADC12IFG0
case 8: break; //Vector 8: ADC12IFG1
case 10: break; //Vector 10: ADC12IFG2
case 12: //Vector 12: ADC12IFG3
//Move A0 results, IFG is cleared
A0results[index] =
ADC12_A_getResults(ADC12_A_BASE,
ADC12_A_MEMORY_0);
//Move A1 results, IFG is cleared
A1results[index] =
ADC12_A_getResults(ADC12_A_BASE,
ADC12_A_MEMORY_1);
//Move A2 results, IFG is cleared
A2results[index] =
ADC12_A_getResults(ADC12_A_BASE,
ADC12_A_MEMORY_2);
//Move A3 results, IFG is cleared
A3results[index] =
ADC12_A_getResults(ADC12_A_BASE,
ADC12_A_MEMORY_3);
//Increment results index, modulo; Set BREAKPOINT here
index++;
if(index == 8)
{
(index = 0);
}
case 14: break; //Vector 14: ADC12IFG4
case 16: break; //Vector 16: ADC12IFG5
case 18: break; //Vector 18: ADC12IFG6
case 20: break; //Vector 20: ADC12IFG7
case 22: break; //Vector 22: ADC12IFG8
case 24: break; //Vector 24: ADC12IFG9
case 26: break; //Vector 26: ADC12IFG10
case 28: break; //Vector 28: ADC12IFG11
case 30: break; //Vector 30: ADC12IFG12
case 32: break; //Vector 32: ADC12IFG13
case 34: break; //Vector 34: ADC12IFG14
default: break;
}
}
__interrupt void USCI_A1_ISR (void)
{
switch (__even_in_range(UCA1IV,4)){
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
//Receive data
Interrupt_UART_ReceiveData_ptr_fuc(USCI_A_UART_receiveData(UART_Module_1_USCI_A_BASEADDRESS));
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
__interrupt void DebugUartIsr(void)
#endif
{
unsigned char ExitLpm = 0;
// Vector 2 - RXIFG; Vector 4 - TXIFG
switch (__even_in_range(UCA3IV, 4))
{
case 2: ExitLpm = TermModeIsr();
default: break;
}
if (ExitLpm) EXIT_LPM_ISR();
}
__interrupt void USCI_B1_ISR(void)
{
switch (__even_in_range(UCB1IV, USCI_SPI_UCTXIFG))
{
case USCI_SPI_UCRXIFG: //Vector 2 - RXIFG
LPM0_EXIT;
break;
case USCI_SPI_UCTXIFG: //Vector 2 - TXIFG
LPM0_EXIT;
break;
default: break;
}
}
__interrupt void RTC_ISR(void)
{
unsigned char ExitLpm = 0;
tMessage Msg;
// compiler intrinsic, value must be even, and in the range of 0 to 10
switch(__even_in_range(RTCIV,10))
{
case RTC_NO_INTERRUPT: break;
case RTC_RDY_IFG: break;
case RTC_EV_IFG: break;
case RTC_A_IFG: break;
case RTC_PRESCALE_ZERO_IFG:
// divide by four to get 32 Hz
if (DivideByFour >= 4-1)
{
DivideByFour = 0;
if (RtcInUseMask & RTC_TIMER_VIBRATION) VibrationMotorStateMachineIsr();
if (RtcInUseMask & RTC_TIMER_BUTTON)
{
SetupMessage(&Msg, ButtonStateMsg, MSG_OPT_NONE);
SendMessageToQueueFromIsr(DISPLAY_QINDEX, &Msg);
ExitLpm = 1;
}
}
else
{
DivideByFour ++;
}
break;
case RTC_PRESCALE_ONE_IFG:
#ifdef DIGITAL
ExitLpm |= LcdRtcUpdateHandlerIsr();
#endif
ExitLpm |= OneSecondTimerHandlerIsr();
break;
default:
break;
}
if (ExitLpm) EXIT_LPM_ISR();
}
__interrupt void Timer_B(void)
{
switch (__even_in_range(TBIV, 14)) // Efficient switch-implementation
{
case 2: // TBCCR1
TBCCR1 += 50000; // Offset until next interrupt
P1OUT ^= 0x01; // Toggle P1.0
break;
case 4:
break; // TBCCR2 not used
case 14:
break; // Overflow not used
}
}
__interrupt void USCI_A1_ISR(void)
{
// printf("www\n");
switch(__even_in_range(UCA1IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA1IFG&UCTXIFG)); // USCI_A1 TX buffer ready?
UCA1TXBUF = UCA1RXBUF; //???????????????????????// // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
__interrupt void USCI_A1_ISR(void)
{
char r;
switch(__even_in_range(UCA1IV,4)){
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
r = UCA1RXBUF;
sendByte(r);
//UCA1TXBUF = UCA1RXBUF; // TX -> RXed character
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
void __attribute__ ((interrupt(RTC_VECTOR))) RTC_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(RTCIV,RTCIV_RTCIF))
{
case RTCIV_NONE: break; // No interrupt
case RTCIV_RTCIF: // RTC Overflow
P1OUT ^= BIT0;
break;
default: break;
}
}
__interrupt void USCI_B0_ISR(void)
{
switch(__even_in_range(UCB0IV,12))
{
case 0: break; // Vector 0: No interrupts
case 2: break; // Vector 2: ALIFG
case 4: break; // Vector 4: NACKIFG
case 6: break; // Vector 6: STTIFG
case 8: break; // Vector 8: STPIFG
case 10: // Vector 10: RXIFG
Count++; // Increment RX byte counter
if (Count)
{
*par.RxData = UCB0RXBUF; // Move RX data to address par.RxData
if ((par.Num_Bytes-Count) == 1) // Only one byte left?
UCB0CTL1 |= UCTXSTP; // Generate I2C stop condition
}
else
{
*PRxData = UCB0RXBUF; // Move final RX data to PRxData
__bic_SR_register_on_exit(LPM0_bits); // Exit active CPU
}
break;
case 12: // Vector 12: TXIFG
if (Count == 0)
{
UCB0TXBUF = par.Instruccion; // Check TX byte counter if counter
// is cero an instruction is transm
if (par.Lec_Esc == 0) // Instruction means reading N Bytes
{
UCB0IE |= UCRXIE; // Enable RX interrupt
UCB0CTL1 |= UCTXSTT; // Repeated I2C start condition
}
}
else
{
if (TXByteCtr <= par.Num_Bytes )
{
UCB0TXBUF = *PTxData++; // Load TX buffer
Count++; // Decrement TX byte counter
}
}
else
{
UCB0CTL1 |= UCTXSTP; // I2C stop condition
UCB0IFG &= ~UCTXIFG; // Clear USCI_B0 TX int flag
__bic_SR_register_on_exit(LPM0_bits); // Exit LPM0
}
}
__interrupt void USCI_A1_ISR(void)
{
short rdata;
switch(__even_in_range(UCA1IV,4)) {
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
while (!(UCA1IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
rdata = UCA1RXBUF;
UCA1TXBUF = rdata; // TX -> RXed character
switch(state) {
case INIT:
switch(rdata) {
case M1:
state = M1;
break;
case M2:
state = M2;
break;
case M3:
state = M3;
break;
case M4:
state = M4;
break;
}
break;
case M1:
TA0CCR4 = rdata; // CCR4 PWM duty cycle
state = INIT;
break;
case M2:
TA0CCR2 = rdata; // CCR4 PWM duty cycle
state = INIT;
break;
case M3:
TA0CCR3 = rdata; // CCR4 PWM duty cycle
state = INIT;
break;
case M4:
TA0CCR4 = rdata; // CCR4 PWM duty cycle
state = INIT;
break;
}
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
__interrupt
#endif
void ADC12ISR(void)
{
switch (__even_in_range(ADC12IV, 34))
{
case 0:
break; // Vector 0: No interrupt
case 2:
break; // Vector 2: ADC overflow
case 4:
break; // Vector 4: ADC timing overflow
case 6: // Vector 6: ADC12IFG0
adc12_result = ADC12MEM0; // Move results, IFG is cleared
adc12_data_ready = 1;
_BIC_SR_IRQ(LPM3_bits); // Exit active CPU
break;
case 8:
break; // Vector 8: ADC12IFG1
case 10:
break; // Vector 10: ADC12IFG2
case 12:
break; // Vector 12: ADC12IFG3
case 14:
break; // Vector 14: ADC12IFG4
case 16:
break; // Vector 16: ADC12IFG5
case 18:
break; // Vector 18: ADC12IFG6
case 20:
break; // Vector 20: ADC12IFG7
case 22:
break; // Vector 22: ADC12IFG8
case 24:
break; // Vector 24: ADC12IFG9
case 26:
break; // Vector 26: ADC12IFG10
case 28:
break; // Vector 28: ADC12IFG11
case 30:
break; // Vector 30: ADC12IFG12
case 32:
break; // Vector 32: ADC12IFG13
case 34:
break; // Vector 34: ADC12IFG14
default:
break;
}
}
__interrupt void TBX_ISR(void)
{
switch (__even_in_range(TBIV, 14)) // Efficient switch-implementation
{
case 2: // TBCCR1
TBCCR1 += 400; // Offset until next interrupt
break;
case 4: // TBCCR2
TBCCR2 += 500; // Offset until next interrupt
break;
case 14: // Overflow
P1OUT ^= 0x01; // Toggle P1.0
break;
}
}
void USCI_A0_ISR(void)
{
Timer_A_disableCaptureCompareInterrupt(TIMER_A1_BASE,TIMER_A_CAPTURECOMPARE_REGISTER_0);
switch(__even_in_range(UCA0IV,4))
{
//Vector 2 - RXIFG
case 2:
A0receivedData = USCI_A_UART_receiveData(USCI_A0_BASE);
break;
default: break;
}
Timer_A_enableCaptureCompareInterrupt(TIMER_A1_BASE,TIMER_A_CAPTURECOMPARE_REGISTER_0);
}
__interrupt void Timer0_A1_ISR(void)
{
switch (__even_in_range(TA0IV, 14)) // Efficient switch-implementation
{
case 2: break; // TA0CCR1 not used
case 4: break; // TA0CCR2 not used
case 6: break; // Reserved
case 8: break; // Reserved
case 10: break; // Reserved
case 12: break; // Reserved
case 14: P1OUT ^= BIT6; // overflow -> Toggle P1.0
break;
}
}
__interrupt void USCI_A1_ISR(void)
{
// P1OUT ^= BIT0;
LPM0_EXIT;
// __bis_SR_register_on_exit(LPM3_bits);
switch(__even_in_range(UCA1IV,4))
{
case 0:break; // Vector 0 - no interrupt
case 2: // Vector 2 - RXIFG
flg_rx = 1;
break;
case 4:break; // Vector 4 - TXIFG
default: break;
}
}
__interrupt void timer0_A1_ISR(void)
{
switch(__even_in_range(TA0IV, 0x14))
{
case TA0IV_NONE: break; // (0x00) None
case TA0IV_TACCR1: break; // (0x02) CCR1 IFG
case TA0IV_TACCR2: break; // (0x04) CCR2 IFG
case TA0IV_3: break; // (0x06) Reserved
case TA0IV_4: break; // (0x08) Reserved
case TA0IV_5: break; // (0x0A) Reserved
case TA0IV_6: break; // (0x0C) Reserved
case TA0IV_TAIFG: break; // (0x0E) TA1IFG - TAR overflow
default: _never_executed();
}
}
__interrupt void Port_4(void)
{
switch(__even_in_range(P4IV,P4IV_P4IFG1))
{
case P4IV_P4IFG0:
StartDebounceTimer();
// disable switch interrupt
DissableSwitch();
break;
default:
break;
}
P4IFG = 0;
}
/*******************************************************************************
* \brief ISR to handle events on the USCI_A1 pins.
*
* \param void
* \return void
******************************************************************************/
void __attribute__ ( ( interrupt(USCI_A1_VECTOR) ) ) hal_debug_uart_isr( void )
{
switch (__even_in_range(UCA1IV,4)) {
case UART_NO_INTERRUPT:
break;
case UART_RX_IFG:
UCA1IFG &= ~UCRXIFG;
UCA1TXBUF = UCA1RXBUF;
break;
case UART_TX_IFG:
break;
default:
break;
}
}
__interrupt void timerB_ISR(void)
{
switch(__even_in_range(TB0IV, 0x14))
{
case TB0IV_NONE: break; // (0x00) None
case TB0IV_TBCCR1: break; // (0x02) CCR1
case TB0IV_TBCCR2: break; // (0x04) CCR2
case TB0IV_TBCCR3: break; // (0x06) CCR3
case TB0IV_TBCCR4: break; // (0x08) CCR4
case TB0IV_TBCCR5: break; // (0x0A) CCR5
case TB0IV_TBCCR6: break; // (0x0C) CCR6
case TB0IV_TBIFG: break; // (0x0E) TA1IFG - TAR overflow
default: _never_executed();
}
}
__interrupt void USCI_B0_ISR(void)
{
switch(__even_in_range(UCB0IV,12))
{
case 0: break; // Vector 0: No interrupts
case 2: break; // Vector 2: ALIFG
case 4: break; // Vector 4: NACKIFG
case 6: break; // Vector 6: STTIFG
case 8: break; // Vector 8: STPIFG
case 10: break; // Vector 10: RXIFG
case 12: // Vector 12: TXIFG
UCB0TXBUF = Inst; // Load Inst in buffer
break;
default: break;
}
}
__interrupt void ADC10_ISR(void)
{
switch(__even_in_range(ADC10IV,12))
{
case 0: break; // No interrupt
case 2: break; // conversion result overflow
case 4: break; // conversion time overflow
case 6: break; // ADC10HI
case 8: break; // ADC10LO
case 10: break; // ADC10IN
case 12: ADC_Result = ADC10MEM0;
__bic_SR_register_on_exit(CPUOFF);
break; // Clear CPUOFF bit from 0(SR)
default: break;
}
}
__interrupt void USCI_A0_ISR(void)
{
switch(__even_in_range(UCA0IV,USCI_UART_UCTXCPTIFG))
{
case USCI_NONE: break;
case USCI_UART_UCRXIFG:
// send it to xbee via UCA1
while(!(UCA1IFG&UCTXIFG));
UCA1TXBUF = UCA0RXBUF; // echo to xbee man
__no_operation();
break;
case USCI_UART_UCTXIFG: break;
case USCI_UART_UCSTTIFG: break;
case USCI_UART_UCTXCPTIFG: break;
}
}
__interrupt void TIMER1_A1_ISR(void)
{
switch(__even_in_range(TA1IV,14))
{
case 0: break; // No interrupt
case 2: break; // CCR1 not used
case 4: break; // CCR2 not used
case 6: break; // reserved
case 8: break; // reserved
case 10: break; // reserved
case 12: break; // reserved
case 14: P1OUT ^= 0x01; // overflow
break;
default: break;
}
}
__interrupt void USCI_A1_ISR(void)
{
switch(__even_in_range(UCA1IV, USCI_UART_UCTXCPTIFG))
{
case USCI_NONE: break;
case USCI_UART_UCRXIFG:
break;
case USCI_UART_UCTXIFG:
// while(!(UCA0IFG&UCTXIFG));
UCA1TXBUF = 0xAA;
__no_operation();
break;
case USCI_UART_UCSTTIFG: break;
case USCI_UART_UCTXCPTIFG: break;
}
}
