uint8_t get_scan_key() {
while (buffer_empty()) {
__halt();
}
interrupt_disabler id{};
return buffer_.pop();
}
// __asm__ blocks are only checked for inline functions that end up being
// emitted, so call functions with __asm__ blocks to make sure their inline
// assembly parses.
void f() {
__movsb(0, 0, 0);
__movsd(0, 0, 0);
__movsw(0, 0, 0);
__stosd(0, 0, 0);
__stosw(0, 0, 0);
#ifdef _M_X64
__movsq(0, 0, 0);
__stosq(0, 0, 0);
#endif
int info[4];
__cpuid(info, 0);
__cpuidex(info, 0, 0);
_xgetbv(0);
__halt();
__nop();
__readmsr(0);
// FIXME: Call these in 64-bit too once the intrinsics have been fixed to
// work there, PR19301
#ifndef _M_X64
__readcr3();
__writecr3(0);
#endif
#ifdef _M_ARM
__dmb(_ARM_BARRIER_ISHST);
#endif
}
int main()
{
//pointer to start of memory location
unsigned int *p = 0x00000000;
//read number of samples
samples = p[0];
// while(1)
{
for( i=OFFSET; i<samples+OFFSET; i++)
{
//unpack the byte values and write on the register
__R30 = (0xFF00 & p[i]) >> 8;
//delay
d++;
d++;
d++;
d++;
d++;
__R30 = (0x00FF & p[i]);
//delay
d++;
d++;
d++;
d++;
d++;
}
}
// Exiting the application - send the interrupt
__R31 = 35; // PRUEVENT_0 on PRU0_R31_VEC_VALID
__halt(); // halt the PRU
}
int main(void)
{
volatile SAMPLE values[NR_CHANNELS];
volatile uint16_t seqno = 0;
volatile uint16_t count = 0;
int idle, channel;
ocp_init();
shm_init();
WR_MAGIC( 0x0ADCDA8A );
WR_SEQNO( seqno );
while (1)
{
// Read ADC data into values
values[0] = adc_read( 0, 0, 0 );
values[1] = adc_read1( 0, 0, 0 );
values[2] = adc_read2( 0, 0, 0 );
values[3] = adc_read3( 0, 0, 0 );
// Write into shared memory
for ( channel = 0; channel < NR_CHANNELS; ++channel ) {
WR_DATA( seqno, channel, count, values[channel] );
}
// Increment and update sample counts
count++;
WR_COUNT( count );
if ( count >= SAMPLES_PER_MSG ) {
count = 0;
WR_COUNT( count );
seqno++;
WR_SEQNO( seqno );
// Signal to host that data is ready for reading
for ( idle=0; idle < 2; ++idle ) {
seqno = seqno;
}
generate_host_interrupt( PRU0_ARM_DONE_INTERRUPT + 16 );
}
// Idle some until time for the next sample
//
// We want a delay of abuot 100us (10kHz) between samples. Since
// the PRU runs at 200MHz (5ns per op), we want 20000 ops for
// an approximate delay of 100us. Since one iteration is
// approximately 10 assembly instructions, counting up to 2000
// for now.
for ( idle=0; idle < 2000; ++idle ) {
seqno = seqno;
}
}
__halt();
return 0;
}
void
dik_show_regs(struct pt_regs *regs, unsigned long *r9_15)
{
printk("pc = [<%016lx>] ra = [<%016lx>] ps = %04lx %s\n",
regs->pc, regs->r26, regs->ps, print_tainted());
print_symbol("pc is at %s\n", regs->pc);
print_symbol("ra is at %s\n", regs->r26 );
printk("v0 = %016lx t0 = %016lx t1 = %016lx\n",
regs->r0, regs->r1, regs->r2);
printk("t2 = %016lx t3 = %016lx t4 = %016lx\n",
regs->r3, regs->r4, regs->r5);
printk("t5 = %016lx t6 = %016lx t7 = %016lx\n",
regs->r6, regs->r7, regs->r8);
if (r9_15) {
printk("s0 = %016lx s1 = %016lx s2 = %016lx\n",
r9_15[9], r9_15[10], r9_15[11]);
printk("s3 = %016lx s4 = %016lx s5 = %016lx\n",
r9_15[12], r9_15[13], r9_15[14]);
printk("s6 = %016lx\n", r9_15[15]);
}
printk("a0 = %016lx a1 = %016lx a2 = %016lx\n",
regs->r16, regs->r17, regs->r18);
printk("a3 = %016lx a4 = %016lx a5 = %016lx\n",
regs->r19, regs->r20, regs->r21);
printk("t8 = %016lx t9 = %016lx t10= %016lx\n",
regs->r22, regs->r23, regs->r24);
printk("t11= %016lx pv = %016lx at = %016lx\n",
regs->r25, regs->r27, regs->r28);
printk("gp = %016lx sp = %p\n", regs->gp, regs+1);
#if 0
__halt();
#endif
}
void main(void) {
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
__delay_cycles(TIME);
// start(TIME);
__delay_cycles(TIME);
while(!(__R31&(1<<3))) {
time = RAM0[0]; // on time
for(i=0; i<time; i++) {
__R30 |= 1<<5;
// __delay_cycles must be passed a const, so we have to do our own loop
// Must have something in loop, otherwise it optimized out.
}
time = RAM0[1]; // off time
for(i=0; i<time; i++) {
__R30 &= ~(1<<5);
}
}
__delay_cycles(TIME); // Give some time for press to release
// Call assembly language
start(RAM0);
__halt();
}
void main()
{
uint32_t gpio;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
gpio = 0x000F;
__R30 = 0x0;
/* Toggle the LEDs */
/* TODO: Create stop condition, else it will toggle indefinitely */
while(1)
{
__R30 ^= gpio;
__delay_cycles(100000000);
}
/* Halt the PRU core - shouldn't get here */
__halt();
}
void main(){
uint32_t *pDdr = (uint32_t *) &CT_DDR;
uint32_t score;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Wait until receipt of interrupt on host 0 */
while((__R31 & 0x40000000) == 0){
}
/* Clear system event in SECR1 */
CT_INTC.SECR1 = 0x1;
/* Clear system event enable in ECR1 */
CT_INTC.ECR1 = 0x1;
/* Point C30 (L3) to 0x3000 offset and C31 (DDR) to 0x0 offset */
PRU0_CTRL.CTPPR1 = 0x00003000;
/* Load value from DDR, decrement, and store it in L3 */
score = pDdr[0];
score--;
CT_L3 = score;
/* Halt PRU core */
__halt();
}
void main()
{
/* Configure GPI and GPO as Mode 0 (Direct Connect) */
CT_CFG.GPCFG0 = 0x0000;
/* Turn on all LEDs */
__R30 = (LED_Group1 | LED_Group2);
/* TODO: Create stop condition, else it will toggle indefinitely */
while(1)
{
/* Both Switch 1 & 2 are pressed */
if( (__R31 & SW1_2) == 0)
__R30 = (LED_Group1 | LED_Group2);
/* Switch 1 is pressed */
else if( (__R31 & SW1) != SW1)
__R30 = LED_Group1;// & ~LED_Group2;
/* Switch 2 is pressed */
else if( (__R31 & SW2) != SW2)
__R30 = LED_Group2;// & ~(LED_Group2);
/* Neither Switch 1/2 are pressed */
else
__R30 = ~(LED_Group1 | LED_Group2);
}
/* Halt the PRU core - shouldn't get here */
__halt();
}
VOID
NTAPI
HaliHaltSystem(VOID)
{
/* Disable interrupts and halt the CPU */
_disable();
__halt();
}
VOID
ExecuteHltInstruction (
IN OUT AMD_CONFIG_PARAMS *StdHeaderPtr
)
{
_disable ();
__halt ();
}
/*
* @implemented
*/
VOID
NTAPI
HalProcessorIdle(VOID)
{
/* Enable interrupts and halt the processor */
_enable();
__halt();
}
void main(){
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Disable counter */
CT_IEP.TMR_GLB_CFG_bit.CNT_ENABLE = 0;
/* Reset Count register */
CT_IEP.TMR_CNT = 0x0;
/* Clear overflow status register */
CT_IEP.TMR_GLB_STS_bit.CNT_OVF = 0x1;
/* Set compare value */
CT_IEP.TMR_CMP0 = 0x77359400; // 10 seconds @ 200MHz
/* Clear compare status */
CT_IEP.TMR_CMP_STS_bit.CMP_HIT = 0xFF;
/* Disable compensation */
CT_IEP.TMR_COMPEN_bit.COMPEN_CNT = 0x0;
/* Enable CMP0 and reset on event */
CT_IEP.TMR_CMP_CFG_bit.CMP0_RST_CNT_EN = 0x1;
CT_IEP.TMR_CMP_CFG_bit.CMP_EN = 0x1;
/* Clear the status of all interrupts */
CT_INTC.SECR0 = 0xFFFFFFFF;
CT_INTC.SECR1 = 0xFFFFFFFF;
/* Enable counter */
CT_IEP.TMR_GLB_CFG = 0x11;
/* Poll until R31.31 is set */
do{
while((__R31 & 0x80000000) == 0){
}
/* Verify that the IEP is the source of the interrupt */
} while ((CT_INTC.SECR0 & (1 << 7)) == 0);
/* Disable counter */
CT_IEP.TMR_GLB_CFG_bit.CNT_ENABLE = 0x0;
/* Disable Compare0 */
CT_IEP.TMR_CMP_CFG = 0x0;
/* Clear Compare status */
CT_IEP.TMR_CMP_STS = 0xFF;
/* Clear the status of the interrupt */
CT_INTC.SECR0 = (1 << 7);
/* Halt the PRU core */
__halt();
}
int main(void)
{
uint32_t result;
volatile uint8_t *ptr_cm;
ptr_cm = CM_PER_BASE;
/*****************************************************************/
/* Access PRU peripherals using Constant Table & PRU header file */
/*****************************************************************/
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Read IEPCLK[OCP_EN] for IEP clock source */
result = CT_CFG.IEPCLK_bit.OCP_EN;
/*****************************************************************/
/* Access SoC peripherals using Constant Table */
/*****************************************************************/
/* Access PRCM (without CT) to initialize McSPI0 clock */
ptr_cm[SPI0_CLKCTRL] = ON;
/* Read McSPI0_MODULCTRL (offset 0x128)*/
result = MCSPI0_MODULCTRL;
/* Toggle MCSPI0_MODULCTRL[MS] (offset 0x128, bit 2) */
MCSPI0_MODULCTRL ^= 0x4;
/* Reset MCSPI0_MODULCTRL[MS] to original value */
MCSPI0_MODULCTRL = result;
/*****************************************************************/
/* Access PRU Shared RAM using Constant Table */
/*****************************************************************/
/* C28 defaults to 0x00000000, we need to set bits 23:8 to 0x0100 in order to have it point to 0x00010000 */
PRU0_CTRL.CTPPR0_bit.C28_POINTER = 0x0100;
/* Define value of shared_freq_1 */
shared_freq_1 = 1;
/* Read PRU Shared RAM Freq_1 memory */
if (shared_freq_1 == 1)
shared_freq_2 = shared_freq_2 + 1;
else
shared_freq_2 = shared_freq_3;
/* Halt PRU core */
__halt();
}
virtual void do_send_packet(const void* data, uint32_t length) override {
REQUIRE(length <= 1500);
if (!(ioreg(reg::STATUS) & STATUS_LU)) {
dbgout() << "[i825x] Link not up. Dropping packet\n";
return;
}
// prepare descriptor
auto& td = tx_desc_[tx_tail_];
tx_tail_ = (tx_tail_ + 1) % num_tx_descriptors;
REQUIRE(td.upper.fields.status == 0);
td.buffer_addr = virt_to_phys(data);
td.lower.data = length | TXD_CMD_RS | TXD_CMD_EOP | TXD_CMD_IFCS;
td.upper.data = 0;
_mm_mfence();
ioreg(reg::TDT0, tx_tail_);
//dbgout() << "Waiting for packet to be sent.\n";
for (uint32_t timeout = 100; !td.upper.fields.status; ) {
__halt();
if (!timeout--) {
#if 0
// Dump stats
constexpr uint32_t nstats = 0x100 / 4;
static uint32_t stats[nstats];
for (uint32_t i = 0; i < nstats; ++i) {
stats[i] += ioreg(static_cast<reg>(0x4000 + i * 4));
dbgout() << as_hex(stats[i]);
dbgout() << ((i % 8 == 7) ? '\n' : ' ');
}
#endif
dbgout() << "Transfer NOT done. Timed out! STATUS = " << as_hex(ioreg(reg::STATUS)) << " TDH = " << ioreg(reg::TDH0) << " TDT " << ioreg(reg::TDT0) << "\n";
#if 0
for (uint32_t i = 0; i < num_tx_descriptors; ++i) {
dbgout() << as_hex(tx_desc_[i].buffer_addr) << " ";
dbgout() << as_hex(tx_desc_[i].lower.data) << " ";
dbgout() << as_hex(tx_desc_[i].upper.data) << " ";
dbgout() << ((i % 3 == 2) ? '\n' : ' ');
}
dbgout() << "\n";
#endif
return;
}
}
//dbgout() << "[i825x] TX Status = " << as_hex(td.upper.fields.status) << "\n";
REQUIRE(td.upper.fields.status == TXD_STAT_DD);
td.upper.data = 0; // Mark ready for re-use
REQUIRE(ioreg(reg::TDH0) == ioreg(reg::TDT0));
}
void main(){
mem1DParams params;
uint8_t *srcPtr;
uint8_t *dstPtr;
uint8_t data;
uint8_t srcBuf[SIZE];
uint8_t dstBuf[SIZE];
buffer.cnt = SIZE;
buffer.src = &srcBuf;
buffer.dst = &dstBuf;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Configure C24 (PRU0 DRAM) and C25 (PRU1 DRAM) offsets as 0x0 */
PRU0_CTRL.CTBIR0 = 0;
PRU0_CTRL.CTBIR1 = 0;
/* Load the MEM1D parameters */
params = buffer;
/* Copy the source and destination addresses into pointers.
* This allows a copy of the entirety of the buffer */
srcPtr = ((uint8_t*)(params.src));
dstPtr = ((uint8_t*)(params.dst));
/* Continue copying until the count is 0 */
while (params.cnt != 0){
/* Load data from source pointer in DRAM into data buffer */
data = *srcPtr;
/* Copy data from data buffer into destination pointer in L3 */
*dstPtr = data;
/* Decrease the count */
params.cnt -= COPY_LENGTH;
/* Update source and destination pointers */
params.src += COPY_LENGTH;
params.dst += COPY_LENGTH;
/* Store current state back into DRAM */
buffer = params;
}
/* Halt PRU core */
__halt();
}
void main(void) {
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
while(!(__R31&(1<<3))) {
__R30 ^= 1<<5;
__delay_cycles(TIME);
// __R30 &= ~(1<<5);
// __delay_cycles(TIME);
}
__delay_cycles(TIME); // Give some time for press to release
// Call assembly language
start(TIME);
__halt();
}
void __panic(const char *fname, const char *format, ...)
{
va_list params;
force_interrupts_off();
stack_trace();
printf("\n\n:: EVIL :: %s() :: ", fname);
va_start(params, format);
__vprintf(format, params);
va_end(params);
while(1) { force_interrupts_off(); __halt(); }
}
int main(){
uint32_t *ddrPtr = (uint32_t *)&CT_DDR;
uint32_t result;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Ensure C31 is pointed to the start of DDR (0 offset) */
PRU0_CTRL.CTPPR1_bit.C31_BLK_POINTER = 0;
/* Read value from DDR, store in the PRU_CFG pin_mx register */
result = *ddrPtr;
CT_CFG.PIN_MX = result;
/* Halt PRU core */
__halt();
}
/*****************************************************************************
Name: Run_RTC_Scheduler
Parameters: none
Returns: none
Description: Starts Round Robin Scheduler. Should be call in Main program after
completing initialization. Only enabled tasks will be scheduled and run.
*****************************************************************************/
void Run_RTC_Scheduler(void)
{
int i;
GBL_run_scheduler = 1;
/* Loop forever */
while (1) {
/* Check each task */
for (i=0 ; i<MAX_TASKS ; i++) {
/* If this is a scheduled task */
if (GBL_task_list[i].task != NULL) { /* valid task */
if (GBL_task_list[i].enabled == 1) { /* enabled */
if (GBL_task_list[i].ready == 1) { /* ready to run */
#if RTC_MONITOR_ACTIVITY
// RTC_ACTIVE_OUTPUT = 0; // Indicate task is active
#endif // RTC_MONITOR_ACTIVITY
/* Run the task */
GBL_task_list[i].task();
#if RTC_MONITOR_ACTIVITY
// RTC_ACTIVE_OUTPUT = 1; // Indicate task is inactive
#endif // RTC_MONITOR_ACTIVITY
/* Reset the task ready flag */
GBL_task_list[i].ready = 0;
break;
}
}
}
}
// reached end of loop, so start at top again
#if RTC_HALT_WHEN_IDLE
RTC_STANDBY_OUTPUT = 0; // Sleeping
__halt();
RTC_STANDBY_OUTPUT = 1; // Not sleeping
#endif // RTC_HALT_WHEN_IDLE
#if RTC_STOP_WHEN_IDLE
RTC_STANDBY_OUTPUT = 0; // Sleeping
__stop();
RTC_STANDBY_OUTPUT = 1; // Not sleeping
#endif // RTC_STOP_WHEN_IDLE
}
}
void NaClAbort(void) {
/*
* We crash the process with a HLT instruction so that the Breakpad
* crash reporter will be invoked when we are running inside Chrome.
*
* This has the disadvantage that an untrusted-code crash will not
* be distinguishable from a trusted-code NaClAbort() based on the
* process's exit status alone
*
* While we could use the INT3 breakpoint instruction to exit (via
* __debugbreak()), that does not work if NaCl's debug exception
* handler is attached, because that always resumes breakpoints (see
* http://code.google.com/p/nativeclient/issues/detail?id=2772).
*/
while (1) {
__halt();
}
}
void main(){
volatile uint32_t gpio;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
/* Toggle GPO pins TODO: Figure out which to use */
gpio = 0x000F;
/* TODO: Create stop condition, else it will toggle indefinitely */
while(1){
__R30 ^= gpio;
__delay_cycles(100000000);
}
/* Halt the PRU core */
__halt();
}
void
pal_init(void)
{
unsigned long i, rev;
struct percpu_struct * percpu;
struct pcb_struct * pcb_pa;
/* */
pcb_va->ksp = 0;
pcb_va->usp = 0;
pcb_va->ptbr = L1[1] >> 32;
pcb_va->asn = 0;
pcb_va->pcc = 0;
pcb_va->unique = 0;
pcb_va->flags = 1;
pcb_va->res1 = 0;
pcb_va->res2 = 0;
pcb_pa = find_pa(VPTB, pcb_va);
/*
*/
srm_printk("Switching to OSF PAL-code .. ");
i = switch_to_osf_pal(2, pcb_va, pcb_pa, VPTB);
if (i) {
srm_printk("failed, code %ld\n", i);
__halt();
}
percpu = (struct percpu_struct *)
(INIT_HWRPB->processor_offset + (unsigned long) INIT_HWRPB);
rev = percpu->pal_revision = percpu->palcode_avail[2];
srm_printk("Ok (rev %lx)\n", rev);
tbia(); /* */
}
void
pal_init(void)
{
unsigned long i, rev;
struct percpu_struct * percpu;
struct pcb_struct * pcb_pa;
/* Create the dummy PCB. */
pcb_va->ksp = 0;
pcb_va->usp = 0;
pcb_va->ptbr = L1[1] >> 32;
pcb_va->asn = 0;
pcb_va->pcc = 0;
pcb_va->unique = 0;
pcb_va->flags = 1;
pcb_va->res1 = 0;
pcb_va->res2 = 0;
pcb_pa = (struct pcb_struct *)find_pa((unsigned long)pcb_va);
/*
* a0 = 2 (OSF)
* a1 = return address, but we give the asm the vaddr of the PCB
* a2 = physical addr of PCB
* a3 = new virtual page table pointer
* a4 = KSP (but the asm sets it)
*/
srm_printk("Switching to OSF PAL-code... ");
i = switch_to_osf_pal(2, pcb_va, pcb_pa, VPTB);
if (i) {
srm_printk("failed, code %ld\n", i);
__halt();
}
percpu = (struct percpu_struct *)
(INIT_HWRPB->processor_offset + (unsigned long) INIT_HWRPB);
rev = percpu->pal_revision = percpu->palcode_avail[2];
srm_printk("OK (rev %lx)\n", rev);
tbia(); /* do it directly in case we are SMP */
}
void main() {
/* Configure GPI and GPO as Mode 0 (Direct Connect) */
CT_CFG.GPCFG0 = 0x0000;
/* Clear GPO pins */
__R30 &= 0xFFFF0000;
/* Configure INTC */
configIntc();
while(1) {
/* Wait for SW1 to be pressed */
if ((__R31 & SW1) != SW1) {
/* Interrupt PRU1, wait 500ms for cheap "debounce" */
/* TODO: Trigger interrupt - see #defines */
}
}
/* Halt the PRU core - shouldn't get here */
__halt();
}
void main(){
/* Configure GPI and GPO as Mode 0 (Direct Connect) */
CT_CFG.GPCFG0 = 0x0000;
/* Clear GPO pins */
__R30 &= 0xFFFF0000;
/* Spin in loop until interrupt on HOST 1 is detected */
while(1){
if (__R31 & HOST1_MASK){
TOGGLE_BLUE;
/* Clear interrupt event */
CT_INTC.SICR = 16; /*TODO: Clear event 16*/;
/* Delay to ensure the event is cleared in INTC */
__delay_cycles(5);
}
}
/* Halt the PRU core - shouldn't get here */
__halt();
}
void main(void)
{
uint32_t *pDdr = (uint32_t *) &CT_DDR;
/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
// Globally enable host interrupts
CT_INTC.GER = 0x1;
/* Clear any pending PRU-generated events */
__R31 = 0x00000000;
/* Start preparing message for host - make sure it's not 0xB */
pDdr[1] = 0x0001;
/* Enable Host interrupt 2 */
CT_INTC.HIEISR |= HOST_NUM;
/* Map channel 2 to host 2 */
CT_INTC.HMR0_bit.HINT_MAP_2 = HOST_NUM;
/* Map PRU0_ARM_INTERRUPT (event 19) to channel 2 */
CT_INTC.CMR4_bit.CH_MAP_19 = CHAN_NUM;
/* Ensure PRU0_ARM_INTERRUPT is cleared */
CT_INTC.SICR = (PRU0_ARM_INTERRUPT - 16);
/* Enable PRU0_ARM_INTERRUPT */
CT_INTC.EISR = (PRU0_ARM_INTERRUPT - 16);
/* Ensure CT_DDR (C31) is pointing to start of DDR memory (0x80000000) */
PRU0_CTRL.CTPPR1_bit.C31_BLK_POINTER = 0x0;
/* Write value of 0xB which Host will read after receiving the interrupt */
pDdr[1] = 0xB;
/* Halt the PRU */
__halt();
}
extern "C" void __cxa_pure_virtual()
{
Debug::debug << "pure virtual\n";
__halt();
}
void main(void)
{
uint32_t i;
volatile uint32_t not_done = 1;
char rxBuffer[6];
rxBuffer[5] = NULL; // null terminate the string
/*** INITIALIZATION ***/
/* Set up UART to function at 115200 baud - DLL divisor is 104 at 16x oversample
* 192MHz / 104 / 16 = ~115200 */
CT_UART.DLL = 104;
CT_UART.DLH = 0;
CT_UART.MDR_bit.OSM_SEL = 0x0;
/* Enable Interrupts in UART module. This allows the main thread to poll for
* Receive Data Available and Transmit Holding Register Empty */
CT_UART.IER = 0x7;
/* If FIFOs are to be used, select desired trigger level and enable
* FIFOs by writing to FCR. FIFOEN bit in FCR must be set first before
* other bits are configured */
/* Enable FIFOs for now at 1-byte, and flush them */
CT_UART.FCR = (0x80) | (0x8) | (0x4) | (0x2) | (0x01); // 8-byte RX FIFO trigger
/* Choose desired protocol settings by writing to LCR */
/* 8-bit word, 1 stop bit, no parity, no break control and no divisor latch */
CT_UART.LCR = 3;
/* If flow control is desired write appropriate values to MCR. */
/* No flow control for now, but enable loopback for test */
#ifdef HWLOOPBACK
CT_UART.MCR = 0x10;
#elif SWLOOPBACK
CT_UART.MCR = 0x00;
#endif
/* Choose desired response to emulation suspend events by configuring
* FREE bit and enable UART by setting UTRST and URRST in PWREMU_MGMT */
/* Allow UART to run free, enable UART TX/RX */
CT_UART.PWREMU_MGMT_bit.FREE = 0x1;
CT_UART.PWREMU_MGMT_bit.URRST = 0x1;
CT_UART.PWREMU_MGMT_bit.UTRST = 0x1;
/* Turn off RTS and CTS functionality */
CT_UART.MCR_bit.AFE = 0x0;
CT_UART.MCR_bit.RTS = 0x0;
/*** END INITIALIZATION ***/
/* Print out greeting message */
PrintMessageOut("Hello you are in the PRU UART demo test please enter 5 characters\r\n");
/* Read in 5 characters from user, then echo them back out */
for (i = 0; i < 5 ; i++) {
rxBuffer[i] = ReadMessageIn();
}
PrintMessageOut("you typed:\r\n");
PrintMessageOut(rxBuffer);
PrintMessageOut("\r\n");
/*** DONE SENDING DATA ***/
/* Disable UART before halting */
CT_UART.PWREMU_MGMT = 0x0;
/* Halt PRU core */
__halt();
}
void
kernel_halt (void)
{
__halt ();
}
