static void idu_irq_unmask(struct irq_data *data) { unsigned long flags; raw_spin_lock_irqsave(&mcip_lock, flags); __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 0); raw_spin_unlock_irqrestore(&mcip_lock, flags); }
static void idu_irq_mask_raw(irq_hw_number_t hwirq) { unsigned long flags; raw_spin_lock_irqsave(&mcip_lock, flags); __mcip_cmd_data(CMD_IDU_SET_MASK, hwirq, 1); raw_spin_unlock_irqrestore(&mcip_lock, flags); }
static void mcip_probe_n_setup(void) { struct mcip_bcr mp; READ_BCR(ARC_REG_MCIP_BCR, mp); sprintf(smp_cpuinfo_buf, "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n", mp.ver, mp.num_cores, IS_AVAIL1(mp.ipi, "IPI "), IS_AVAIL1(mp.idu, "IDU "), IS_AVAIL1(mp.dbg, "DEBUG "), IS_AVAIL1(mp.gfrc, "GFRC")); cpuinfo_arc700[0].extn.gfrc = mp.gfrc; if (mp.dbg) { __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); } }
void mcip_init_early_smp(void) { #define IS_AVAIL1(var, str) ((var) ? str : "") struct mcip_bcr { #ifdef CONFIG_CPU_BIG_ENDIAN unsigned int pad3:8, idu:1, llm:1, num_cores:6, iocoh:1, grtc:1, dbg:1, pad2:1, msg:1, sem:1, ipi:1, pad:1, ver:8; #else unsigned int ver:8, pad:1, ipi:1, sem:1, msg:1, pad2:1, dbg:1, grtc:1, iocoh:1, num_cores:6, llm:1, idu:1, pad3:8; #endif } mp; READ_BCR(ARC_REG_MCIP_BCR, mp); sprintf(smp_cpuinfo_buf, "Extn [SMP]\t: ARConnect (v%d): %d cores with %s%s%s%s\n", mp.ver, mp.num_cores, IS_AVAIL1(mp.ipi, "IPI "), IS_AVAIL1(mp.idu, "IDU "), IS_AVAIL1(mp.dbg, "DEBUG "), IS_AVAIL1(mp.grtc, "GRTC")); idu_detected = mp.idu; if (mp.dbg) { __mcip_cmd_data(CMD_DEBUG_SET_SELECT, 0, 0xf); __mcip_cmd_data(CMD_DEBUG_SET_MASK, 0xf, 0xf); } if (IS_ENABLED(CONFIG_ARC_HAS_GRTC) && !mp.grtc) panic("kernel trying to use non-existent GRTC\n"); }
static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl, unsigned int distr) { union { unsigned int word; struct { unsigned int distr:2, pad:2, lvl:1, pad2:27; }; } data; data.distr = distr; data.lvl = lvl; __mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word); }
/* * Set the DEST for @cmn_irq to @cpu_mask (1 bit per core) */ static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask) { __mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask); }