StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
uint32_t *pulUpperCSA = NULL;
uint32_t *pulLowerCSA = NULL;
/* 16 Address Registers (4 Address registers are global), 16 Data
Registers, and 3 System Registers.
There are 3 registers that track the CSAs.
FCX points to the head of globally free set of CSAs.
PCX for the task needs to point to Lower->Upper->NULL arrangement.
LCX points to the last free CSA so that corrective action can be taken.
Need two CSAs to store the context of a task.
The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
The Lower Context points to the Upper Context ready for the return from the interrupt handler.
The Real stack pointer for the task is stored in the A10 which is restored
with the upper context. */
/* Have to disable interrupts here because the CSAs are going to be
manipulated. */
portENTER_CRITICAL();
{
/* DSync to ensure that buffering is not a problem. */
_dsync();
/* Consume two free CSAs. */
pulLowerCSA = portCSA_TO_ADDRESS( _mfcr( $FCX ) );
if( NULL != pulLowerCSA )
{
/* The Lower Links to the Upper. */
pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
}
/* Check that we have successfully reserved two CSAs. */
if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
{
/* Remove the two consumed CSAs from the free CSA list. */
_disable();
_dsync();
_mtcr( $FCX, pulUpperCSA[ 0 ] );
_isync();
_enable();
}
else
{
/* Simply trigger a context list depletion trap. */
_svlcx();
}
}
portEXIT_CRITICAL();
/* Clear the upper CSA. */
memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
/* Upper Context. */
pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
/* Clear the lower CSA. */
memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
/* Lower Context. */
pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
/* PCXI pointing to the Upper context. */
pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
/* Save the link to the CSA in the top of stack. */
pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
/* DSync to ensure that buffering is not a problem. */
_dsync();
return pxTopOfStack;
}
int32_t xPortStartScheduler( void )
{
extern void vTrapInstallHandlers( void );
uint32_t ulMFCR = 0UL;
uint32_t *pulUpperCSA = NULL;
uint32_t *pulLowerCSA = NULL;
/* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
when this function is called. */
/* Set-up the timer interrupt. */
prvSetupTimerInterrupt();
/* Install the Trap Handlers. */
vTrapInstallHandlers();
/* Install the Syscall Handler for yield calls. */
if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
{
/* Failed to install the yield handler, force an assert. */
configASSERT( ( ( volatile void * ) NULL ) );
}
/* Enable then install the priority 1 interrupt for pending context
switches from an ISR. See mod_SRC in the TriCore manual. */
CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
{
/* Failed to install the yield handler, force an assert. */
configASSERT( ( ( volatile void * ) NULL ) );
}
_disable();
/* Load the initial SYSCON. */
_mtcr( $SYSCON, portINITIAL_SYSCON );
_isync();
/* ENDINIT has already been applied in the 'cstart.c' code. */
/* Clear the PSW.CDC to enable the use of an RFE without it generating an
exception because this code is not genuinely in an exception. */
ulMFCR = _mfcr( $PSW );
ulMFCR &= portRESTORE_PSW_MASK;
_dsync();
_mtcr( $PSW, ulMFCR );
_isync();
/* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
_dsync();
_mtcr( $PCXI, *pxCurrentTCB );
_isync();
_nop();
_rslcx();
_nop();
/* Return to the first task selected to execute. */
__asm volatile( "rfe" );
/* Will not get here. */
return 0;
}
static void prvSystemTickHandler( int iArg )
{
unsigned long ulSavedInterruptMask;
unsigned long *pxUpperCSA = NULL;
unsigned long xUpperCSA = 0UL;
extern volatile unsigned long *pxCurrentTCB;
long lYieldRequired;
/* Just to avoid compiler warnings about unused parameters. */
( void ) iArg;
/* Clear the interrupt source. */
STM_ISRR.reg = 1UL;
/* Reload the Compare Match register for X ticks into the future.
If critical section or interrupt nesting budgets are exceeded, then
it is possible that the calculated next compare match value is in the
past. If this occurs (unlikely), it is possible that the resulting
time slippage will exceed a single tick period. Any adverse effect of
this is time bounded by the fact that only the first n bits of the 56 bit
STM timer are being used for a compare match, so another compare match
will occur after an overflow in just those n bits (not the entire 56 bits).
As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
a missed tick could result in the next tick interrupt occurring within a
time that is 1.7 times the desired period. The fact that this is greater
than a single tick period is an effect of using a timer that cannot be
automatically reset, in hardware, by the occurrence of a tick interrupt.
Changing the tick source to a timer that has an automatic reset on compare
match (such as a GPTA timer) will reduce the maximum possible additional
period to exactly 1 times the desired period. */
STM_CMP0.reg += ulCompareMatchValue;
/* Kernel API calls require Critical Sections. */
ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
{
/* Increment the Tick. */
lYieldRequired = xTaskIncrementTick();
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
if( lYieldRequired != pdFALSE )
{
/* Save the context of a task.
The upper context is automatically saved when entering a trap or interrupt.
Need to save the lower context as well and copy the PCXI CSA ID into
pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
TCB of a task.
Call vTaskSwitchContext to select the next task, note that this changes the
value of pxCurrentTCB so that it needs to be reloaded.
Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
that has just been switched in.
Load the context of the task.
Need to restore the lower context by loading the CSA from
pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
In the Interrupt handler post-amble, RSLCX will restore the lower context
of the task. RFE will restore the upper context of the task, jump to the
return address and restore the previous state of interrupts being
enabled/disabled. */
_disable();
_dsync();
xUpperCSA = _mfcr( $PCXI );
pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
*pxCurrentTCB = pxUpperCSA[ 0 ];
vTaskSwitchContext();
pxUpperCSA[ 0 ] = *pxCurrentTCB;
CPU_SRC0.bits.SETR = 0;
_isync();
}
}