void test_arm_irq_vector_table(void) { printk("Test Cortex-M3 IRQ installed directly in vector table\n"); for (int ii = 0; ii < 3; ii++) { irq_enable(ii); _irq_priority_set(ii, 0, 0); k_sem_init(&sem[ii], 0, UINT_MAX); } zassert_true((k_sem_take(&sem[0], K_NO_WAIT) || k_sem_take(&sem[1], K_NO_WAIT) || k_sem_take(&sem[2], K_NO_WAIT)), NULL); for (int ii = 0; ii < 3; ii++) { #if defined(CONFIG_SOC_TI_LM3S6965_QEMU) /* the QEMU does not simulate the * STIR register: this is a workaround */ NVIC_SetPendingIRQ(ii); #else NVIC->STIR = ii; #endif } zassert_false((k_sem_take(&sem[0], K_NO_WAIT) || k_sem_take(&sem[1], K_NO_WAIT) || k_sem_take(&sem[2], K_NO_WAIT)), NULL); }
void test_irq_vector_table(void) { printk("Test Cortex-M3 IRQ installed directly in vector table\n"); for (int ii = 0; ii < 3; ii++) { irq_enable(ii); _irq_priority_set(ii, 0, 0); k_sem_init(&sem[ii], 0, UINT_MAX); } assert_true((k_sem_take(&sem[0], K_NO_WAIT) || k_sem_take(&sem[1], K_NO_WAIT) || k_sem_take(&sem[2], K_NO_WAIT)), NULL); for (int ii = 0; ii < 3; ii++) { _NvicSwInterruptTrigger(ii); } assert_false((k_sem_take(&sem[0], K_NO_WAIT) || k_sem_take(&sem[1], K_NO_WAIT) || k_sem_take(&sem[2], K_NO_WAIT)), NULL); }