/* ------------- interrupt handling below ------------------ */
static void mali_pp_irq_probe_trigger(void *data)
{
struct mali_pp_core *core = (struct mali_pp_core *)data;
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MASK_USED);
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT, MALI200_REG_VAL_IRQ_BUS_ERROR);
_mali_osk_mem_barrier();
}
static void mali_pp_irq_probe_trigger(void *data)
{
struct mali_pp_core *core = (struct mali_pp_core *)data;
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_MASK, MALI200_REG_VAL_IRQ_MASK_USED); /* @@@@ This should not be needed */
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_RAWSTAT, MALI200_REG_VAL_IRQ_FORCE_HANG);
_mali_osk_mem_barrier();
}
/* ------------- interrupt handling below ------------------ */
static void mali_gp_irq_probe_trigger(void *data)
{
struct mali_gp_core *core = (struct mali_gp_core *)data;
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_MASK, MALIGP2_REG_VAL_IRQ_MASK_USED);
mali_hw_core_register_write(&core->hw_core, MALIGP2_REG_ADDR_MGMT_INT_RAWSTAT, MALIGP2_REG_VAL_CMD_FORCE_HANG);
_mali_osk_mem_barrier();
}
static _mali_osk_errcode_t fill_page(mali_io_address mapping, u32 data)
{
int i;
MALI_DEBUG_ASSERT_POINTER(mapping);
for (i = 0; i < MALI_MMU_PAGE_SIZE / 4; i++) {
_mali_osk_mem_iowrite32_relaxed(mapping, i * sizeof(u32), data);
}
_mali_osk_mem_barrier();
MALI_SUCCESS;
}
static _mali_osk_errcode_t mali_pp_irq_probe_ack(void *data)
{
struct mali_pp_core *core = (struct mali_pp_core *)data;
u32 irq_readout;
irq_readout = mali_hw_core_register_read(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_STATUS);
if (MALI200_REG_VAL_IRQ_BUS_ERROR & irq_readout) {
mali_hw_core_register_write(&core->hw_core, MALI200_REG_ADDR_MGMT_INT_CLEAR, MALI200_REG_VAL_IRQ_BUS_ERROR);
_mali_osk_mem_barrier();
return _MALI_OSK_ERR_OK;
}
return _MALI_OSK_ERR_FAULT;
}
void mali_pp_job_start(struct mali_pp_core *core, struct mali_pp_job *job, u32 sub_job)
{
u32 *frame_registers = mali_pp_job_get_frame_registers(job);
u32 *wb0_registers = mali_pp_job_get_wb0_registers(job);
u32 *wb1_registers = mali_pp_job_get_wb1_registers(job);
u32 *wb2_registers = mali_pp_job_get_wb2_registers(job);
core->counter_src0_used = core->counter_src0;
core->counter_src1_used = core->counter_src1;
MALI_DEBUG_ASSERT_POINTER(core);
MALI_ASSERT_GROUP_LOCKED(core->group);
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_FRAME, frame_registers, MALI200_NUM_REGS_FRAME, mali_frame_registers_reset_values);
_mali_osk_mem_barrier();
if (0 != sub_job)
{
/*
* There are two frame registers which are different for each sub job.
* For the first sub job, these are correctly represented in the frame register array,
* but we need to patch these for all other sub jobs
*/
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_FRAME, mali_pp_job_get_addr_frame(job, sub_job));
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_STACK, mali_pp_job_get_addr_stack(job, sub_job), mali_frame_registers_reset_values[MALI200_REG_ADDR_STACK/4]);
}
if (wb0_registers[0]) /* M200_WB0_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, wb0_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB0, 0, mali_wb_registers_reset_values[0] );
}
if (wb1_registers[0]) /* M200_WB1_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, wb1_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB1, 0, mali_wb_registers_reset_values[0] );
}
if (wb2_registers[0]) /* M200_WB2_REG_SOURCE_SELECT register */
{
mali_hw_core_register_write_array_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, wb2_registers, MALI200_NUM_REGS_WBx, mali_wb_registers_reset_values);
}
else
{
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_WB2, 0, mali_wb_registers_reset_values[0] );
}
/* This selects which performance counters we are reading */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used || MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
/* global_config has enabled HW counters, this will override anything specified by user space */
if (MALI_HW_CORE_NO_COUNTER != core->counter_src0_used)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (MALI_HW_CORE_NO_COUNTER != core->counter_src1_used)
{
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
}
else
{
/* Use HW counters from job object, if any */
u32 perf_counter_flag = mali_pp_job_get_perf_counter_flag(job);
if (0 != perf_counter_flag)
{
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
core->counter_src0_used = mali_pp_job_get_perf_counter_src0(job);
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC, core->counter_src0_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
if (perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
core->counter_src1_used = mali_pp_job_get_perf_counter_src1(job);
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC, core->counter_src1_used);
mali_hw_core_register_write_relaxed_conditional(&core->hw_core, MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE, MALI200_REG_VAL_PERF_CNT_ENABLE, mali_perf_cnt_enable_reset_value);
}
}
}
MALI_DEBUG_PRINT(3, ("Mali PP: Starting job 0x%08X part %u/%u on PP core %s\n", job, sub_job + 1, mali_pp_job_get_sub_job_count(job), core->hw_core.description));
/* Adding barrier to make sure all rester writes are finished */
_mali_osk_write_mem_barrier();
/* This is the command that starts the core. */
mali_hw_core_register_write_relaxed(&core->hw_core, MALI200_REG_ADDR_MGMT_CTRL_MGMT, MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
/* Adding barrier to make sure previous rester writes is finished */
_mali_osk_write_mem_barrier();
/* Setup the timeout timer value and save the job id for the job running on the pp core */
_mali_osk_timer_add(core->timeout_timer, _mali_osk_time_mstoticks(mali_max_job_runtime));
core->timeout_job_id = mali_pp_job_get_id(job);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_SINGLE | MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id) | MALI_PROFILING_EVENT_REASON_SINGLE_HW_FLUSH, mali_pp_job_get_frame_builder_id(job), mali_pp_job_get_flush_id(job), 0, 0, 0);
_mali_osk_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_id), mali_pp_job_get_pid(job), mali_pp_job_get_tid(job), 0, 0, 0);
#endif
core->running_job = job;
core->running_sub_job = sub_job;
}
/* Start this job on this core. Return MALI_TRUE if the job was started. */
static _mali_osk_errcode_t subsystem_mali200_start_job(mali_core_job * job, mali_core_renderunit * core)
{
mali200_job *job200;
/* The local extended version of the general structs */
job200 = _MALI_OSK_CONTAINER_OF(job, mali200_job, embedded_core_job);
if ( (0 == job200->user_input.frame_registers[0]) ||
(0 == job200->user_input.frame_registers[1]) )
{
MALI_DEBUG_PRINT(4, ("Mali PP: Job: 0x%08x WILL NOT START SINCE JOB HAS ILLEGAL ADDRESSES\n",
(u32)job200->user_input.user_job_ptr));
MALI_ERROR(_MALI_OSK_ERR_FAULT);
}
MALI_DEBUG_PRINT(4, ("Mali PP: Job: 0x%08x START_RENDER Tile_list: 0x%08x\n",
(u32)job200->user_input.user_job_ptr,
job200->user_input.frame_registers[0]));
MALI_DEBUG_PRINT(6, ("Mali PP: RSW base addr: 0x%08x Vertex base addr: 0x%08x\n",
job200->user_input.frame_registers[1], job200->user_input.frame_registers[2]));
/* Frame registers. Copy from mem to physical registers */
mali_core_renderunit_register_write_array(
core,
MALI200_REG_ADDR_FRAME,
&(job200->user_input.frame_registers[0]),
MALI200_NUM_REGS_FRAME);
/* Write Back unit 0. Copy from mem to physical registers*/
mali_core_renderunit_register_write_array(
core,
MALI200_REG_ADDR_WB0,
&(job200->user_input.wb0_registers[0]),
MALI200_NUM_REGS_WBx);
/* Write Back unit 1. Copy from mem to physical registers */
mali_core_renderunit_register_write_array(
core,
MALI200_REG_ADDR_WB1,
&(job200->user_input.wb1_registers[0]),
MALI200_NUM_REGS_WBx);
/* Write Back unit 2. Copy from mem to physical registers */
mali_core_renderunit_register_write_array(
core,
MALI200_REG_ADDR_WB2,
&(job200->user_input.wb2_registers[0]),
MALI200_NUM_REGS_WBx);
/* This selects which performance counters we are reading */
if ( 0 != job200->user_input.perf_counter_flag )
{
if ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC0_ENABLE)
{
mali_core_renderunit_register_write(
core,
MALI200_REG_ADDR_MGMT_PERF_CNT_0_ENABLE,
MALI200_REG_VAL_PERF_CNT_ENABLE);
mali_core_renderunit_register_write(
core,
MALI200_REG_ADDR_MGMT_PERF_CNT_0_SRC,
job200->user_input.perf_counter_src0);
}
if ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_SRC1_ENABLE)
{
mali_core_renderunit_register_write(
core,
MALI200_REG_ADDR_MGMT_PERF_CNT_1_ENABLE,
MALI200_REG_VAL_PERF_CNT_ENABLE);
mali_core_renderunit_register_write(
core,
MALI200_REG_ADDR_MGMT_PERF_CNT_1_SRC,
job200->user_input.perf_counter_src1);
}
#if defined(USING_MALI400_L2_CACHE)
if ( job200->user_input.perf_counter_flag & (_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE|_MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE) )
{
int force_reset = ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_RESET ) ? 1 : 0;
u32 src0 = 0;
u32 src1 = 0;
if ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC0_ENABLE )
{
src0 = job200->user_input.perf_counter_l2_src0;
}
if ( job200->user_input.perf_counter_flag & _MALI_PERFORMANCE_COUNTER_FLAG_L2_SRC1_ENABLE )
{
src1 = job200->user_input.perf_counter_l2_src1;
}
mali_kernel_l2_cache_set_perf_counters(src0, src1, force_reset); /* will activate and possibly reset counters */
/* Now, retrieve the current values, so we can substract them when the job has completed */
mali_kernel_l2_cache_get_perf_counters(&job200->perf_counter_l2_src0,
&job200->perf_counter_l2_val0,
&job200->perf_counter_l2_src1,
&job200->perf_counter_l2_val1);
}
#endif
}
subsystem_flush_mapped_mem_cache();
_mali_osk_mem_barrier();
#if MALI_STATE_TRACKING
_mali_osk_atomic_inc(&job->session->jobs_started);
#endif
/* This is the command that starts the Core */
mali_core_renderunit_register_write(
core,
MALI200_REG_ADDR_MGMT_CTRL_MGMT,
MALI200_REG_VAL_CTRL_MGMT_START_RENDERING);
#if MALI_TIMELINE_PROFILING_ENABLED
_mali_profiling_add_event(MALI_PROFILING_EVENT_TYPE_START|MALI_PROFILING_MAKE_EVENT_CHANNEL_PP(core->core_number), job200->pid, job200->tid, 0, 0, 0);
#endif
MALI_SUCCESS;
}
