int omap2_dflt_clk_enable(struct clk *clk) { u32 v; if (unlikely(clk->enable_reg == NULL)) { pr_err("clock.c: Enable for %s without enable code\n", clk->name); return 0; /* REVISIT: -EINVAL */ } v = __raw_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); __raw_writel(v, clk->enable_reg); v = __raw_readl(clk->enable_reg); /* OCP barrier */ if (clk->ops->find_idlest) { if (cpu_is_omap44xx()) _omap4_module_wait_ready(clk); else _omap2_module_wait_ready(clk); } return 0; }
/** * omap2_dflt_clk_enable - enable a clock in the hardware * @hw: struct clk_hw * of the clock to enable * * Enable the clock @hw in the hardware. We first call into the OMAP * clockdomain code to "enable" the corresponding clockdomain if this * is the first enabled user of the clockdomain. Then program the * hardware to enable the clock. Then wait for the IP block that uses * this clock to leave idle (if applicable). Returns the error value * from clkdm_clk_enable() if it terminated with an error, or -EINVAL * if @hw has a null clock enable_reg, or zero upon success. */ int omap2_dflt_clk_enable(struct clk_hw *hw) { struct clk_hw_omap *clk; u32 v; int ret = 0; bool clkdm_control; if (ti_clk_get_features()->flags & TI_CLK_DISABLE_CLKDM_CONTROL) clkdm_control = false; else clkdm_control = true; clk = to_clk_hw_omap(hw); if (clkdm_control && clk->clkdm) { ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); if (ret) { WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); return ret; } } if (IS_ERR(clk->enable_reg)) { pr_err("%s: %s missing enable_reg\n", __func__, clk_hw_get_name(hw)); ret = -EINVAL; goto err; } /* FIXME should not have INVERT_ENABLE bit here */ v = ti_clk_ll_ops->clk_readl(clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); ti_clk_ll_ops->clk_writel(v, clk->enable_reg); v = ti_clk_ll_ops->clk_readl(clk->enable_reg); /* OCP barrier */ if (clk->ops && clk->ops->find_idlest) _omap2_module_wait_ready(clk); return 0; err: if (clkdm_control && clk->clkdm) ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); return ret; }
/** * omap2_dflt_clk_enable - enable a clock in the hardware * @hw: struct clk_hw * of the clock to enable * * Enable the clock @hw in the hardware. We first call into the OMAP * clockdomain code to "enable" the corresponding clockdomain if this * is the first enabled user of the clockdomain. Then program the * hardware to enable the clock. Then wait for the IP block that uses * this clock to leave idle (if applicable). Returns the error value * from clkdm_clk_enable() if it terminated with an error, or -EINVAL * if @hw has a null clock enable_reg, or zero upon success. */ int omap2_dflt_clk_enable(struct clk_hw *hw) { struct clk_hw_omap *clk; u32 v; int ret = 0; clk = to_clk_hw_omap(hw); if (clkdm_control && clk->clkdm) { ret = clkdm_clk_enable(clk->clkdm, hw->clk); if (ret) { WARN(1, "%s: could not enable %s's clockdomain %s: %d\n", __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret); return ret; } } if (unlikely(clk->enable_reg == NULL)) { pr_err("%s: %s missing enable_reg\n", __func__, __clk_get_name(hw->clk)); ret = -EINVAL; goto err; } /* FIXME should not have INVERT_ENABLE bit here */ v = omap2_clk_readl(clk, clk->enable_reg); if (clk->flags & INVERT_ENABLE) v &= ~(1 << clk->enable_bit); else v |= (1 << clk->enable_bit); omap2_clk_writel(v, clk, clk->enable_reg); v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */ if (clk->ops && clk->ops->find_idlest) _omap2_module_wait_ready(clk); return 0; err: if (clkdm_control && clk->clkdm) clkdm_clk_disable(clk->clkdm, hw->clk); return ret; }