コード例 #1
0
int
smap_intr(void *arg)
{
	struct smap_softc *sc = arg;
	struct ifnet *ifp;
	u_int16_t cause, disable, r;

	cause = _reg_read_2(SPD_INTR_STATUS_REG16) &
	    _reg_read_2(SPD_INTR_ENABLE_REG16);

	disable = cause & (SPD_INTR_RXDNV | SPD_INTR_TXDNV);
	if (disable) {
		r = _reg_read_2(SPD_INTR_ENABLE_REG16);
		r &= ~disable;
		_reg_write_2(SPD_INTR_ENABLE_REG16, r);

		printf("%s: invalid descriptor. (%c%c)\n", DEVNAME,
		    disable & SPD_INTR_RXDNV ? 'R' : '_',
		    disable & SPD_INTR_TXDNV ? 'T' : '_');

		if (disable & SPD_INTR_RXDNV)
			smap_rxeof(arg);

		_reg_write_2(SPD_INTR_CLEAR_REG16, disable);
	}

	if (cause & SPD_INTR_TXEND) {
		_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_TXEND);
		if (_reg_read_1(SMAP_RXFIFO_FRAME_REG8) > 0)
			cause |= SPD_INTR_RXEND;
		smap_txeof(arg);
	}

	if (cause & SPD_INTR_RXEND) {
		_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND);
		smap_rxeof(arg);
		if (sc->tx_desc_cnt > 0 &&
		    sc->tx_desc_cnt > _reg_read_1(SMAP_TXFIFO_FRAME_REG8))
			smap_txeof(arg);
	}

	if (cause & SPD_INTR_EMAC3)
		emac3_intr(arg);
	
	/* if transmission is pending, start here */
	ifp = &sc->ethercom.ec_if;
	if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
		smap_start(ifp);
#if NRND > 0
	rnd_add_uint32(&sc->rnd_source, cause | sc->tx_fifo_ptr << 16);
#endif

	return (1);
}
コード例 #2
0
ファイル: sbus.c プロジェクト: MarginC/kame
/* SCPH-18000 */
void
sbus_type2_pcmcia_intr_clear()
{

	if (_reg_read_2(SBUS_PCMCIA_CSC1_REG16) & 0x080)
		_reg_write_2(SBUS_PCMCIA_CSC1_REG16, 0xffff);
}
コード例 #3
0
ファイル: sbus.c プロジェクト: MarginC/kame
void
sbus_type3_pcmcia_intr_reinstall()
{
	u_int16_t r = _reg_read_2(SBUS_PCMCIA3_TIMR_REG16);

	_reg_write_2(SBUS_PCMCIA3_TIMR_REG16, 1);
	_reg_write_2(SBUS_PCMCIA3_TIMR_REG16, r);
}
コード例 #4
0
ファイル: sh4_dev.cpp プロジェクト: MarginC/kame
void
SH4dev::hd64465_dump()
{

    DPRINTF((TEXT("<<<HD64465>>>\n")));
    if (_reg_read_2(HD64465_SDIDR) != 0x8122) {
        DPRINTF((TEXT("not found.\n")));
        return;
    }

    DPRINTF((TEXT("SMSCR:  ")));	// standby
    bitdisp(_reg_read_2(HD64465_SMSCR));
    DPRINTF((TEXT("SPCCR:  ")));	// clock
    bitdisp(_reg_read_2(HD64465_SPCCR));

    DPRINTF((TEXT("\nNIRR:   ")));	// request
    bitdisp(_reg_read_2(HD64465_NIRR));
    DPRINTF((TEXT("NIMR:   ")));	// mask
    bitdisp(_reg_read_2(HD64465_NIMR));
    DPRINTF((TEXT("NITR:   ")));	// trigger
    bitdisp(_reg_read_2(HD64465_NITR));

#if 0 // monitoring HD64465 interrupt request.
    suspendIntr();
    while (1)
        bitdisp(_reg_read_2(HD64465_NIRR));
    /* NOTREACHED */
#endif
}
コード例 #5
0
ファイル: wdc_spd.c プロジェクト: lacombar/netbsd-alc
void
__wdc_spd_disable()
{
	u_int16_t r;

	r = _reg_read_2(SPD_INTR_ENABLE_REG16);
	r &= ~SPD_INTR_HDD;
	_reg_write_2(SPD_INTR_ENABLE_REG16, r);
}
コード例 #6
0
void
SH3dev::icu_control()
{
	const char *sense_select[] = {
		"falling edge",
		"raising edge",
		"low level",
		"reserved",
	};
	uint16_t r;

	// PINT0-15
	DPRINTF((TEXT("PINT enable(on |)  :")));
	bitdisp(_reg_read_2(SH3_PINTER));
	DPRINTF((TEXT("PINT detect(high |):")));
	bitdisp(_reg_read_2(SH3_ICR2));
	// NMI
	r = _reg_read_2(SH3_ICR0);
	DPRINTF((TEXT("NMI(%S %S-edge),"),
	    r & SH3_ICR0_NMIL ? "High" : "Low",
	    r & SH3_ICR0_NMIE ? "raising" : "falling"));
	r = _reg_read_2(SH3_ICR1);
	DPRINTF((TEXT(" %S maskable,"), r & SH3_ICR1_MAI ? "" : "never"));
	DPRINTF((TEXT("  SR.BL %S\n"),
	    r & SH3_ICR1_BLMSK ? "ignored" : "maskable"));
	// IRQ0-5
	DPRINTF((TEXT("IRQ[3:0]pin : %S mode\n"),
	    r & SH3_ICR1_IRQLVL ? "IRL 15level" : "IRQ[0:3]"));
	if (r & SH3_ICR1_IRQLVL) {
		DPRINTF((TEXT("IRLS[0:3] %S\n"),
		    r & SH3_ICR1_IRLSEN ? "enabled" : "disabled"));
	}
	// sense select
	for (int i = 5; i >= 0; i--) {
		DPRINTF((TEXT("IRQ[%d] %S\n"), i,
		    sense_select [
			    (r >>(i * 2)) & SH3_SENSE_SELECT_MASK]));
	}
}
コード例 #7
0
void
SH3dev::icu_dump()
{

	super::icu_dump_priority(_ipr_table);
	icu_control();
	DPRINTF((TEXT("ICR0   0x%08x\n"), _reg_read_2(SH3_ICR0)));
	DPRINTF((TEXT("ICR1   0x%08x\n"), _reg_read_2(SH3_ICR1)));
	DPRINTF((TEXT("ICR2   0x%08x\n"), _reg_read_2(SH3_ICR2)));
	DPRINTF((TEXT("PINTER 0x%08x\n"), _reg_read_2(SH3_PINTER)));
	DPRINTF((TEXT("IPRA   0x%08x\n"), _reg_read_2(SH3_IPRA)));
	DPRINTF((TEXT("IPRB   0x%08x\n"), _reg_read_2(SH3_IPRB)));
	DPRINTF((TEXT("IPRC   0x%08x\n"), _reg_read_2(SH3_IPRC)));
	DPRINTF((TEXT("IPRD   0x%08x\n"), _reg_read_2(SH3_IPRD)));
	DPRINTF((TEXT("IPRE   0x%08x\n"), _reg_read_2(SH3_IPRE)));
	DPRINTF((TEXT("IRR0   0x%08x\n"), _reg_read_1(SH3_IRR0)));
	DPRINTF((TEXT("IRR1   0x%08x\n"), _reg_read_1(SH3_IRR1)));
	DPRINTF((TEXT("IRR2   0x%08x\n"), _reg_read_1(SH3_IRR2)));
}
コード例 #8
0
ファイル: sh4_dev.cpp プロジェクト: MarginC/kame
// INTC
void
SH4dev::icu_dump()
{
#define ON(x, c)	((x) & (c) ? check[1] : check[0])
#define _(n)		DPRINTF((TEXT("%S %S "), #n, ON(r, SH4_ICR_ ## n)))
    static const char *check[] = { "[_]", "[x]" };
    u_int16_t r;

    super::icu_dump_priority(_ipr_table);

    r = _reg_read_2(SH4_ICR);
    DPRINTF((TEXT("ICR: ")));
    _(NMIL);
    _(MAI);
    _(NMIB);
    _(NMIE);
    _(IRLM);
    DPRINTF((TEXT("0x%04x\n"), r));

#if 0 // monitoring SH4 interrupt request.
    // disable SH3 internal devices interrupt.
    suspendIntr();
    _reg_write_2(SH4_IPRA, 0);
    _reg_write_2(SH4_IPRB, 0);
    _reg_write_2(SH4_IPRC, 0);
//	_reg_write_2(SH4_IPRD, 0);  SH7709S only.
    resumeIntr(0);	// all interrupts enable.
    while (1) {
        DPRINTF((TEXT("%04x ", _reg_read_2(HD64465_NIRR))));
        bitdisp(_reg_read_4(SH4_INTEVT));
    }
    /* NOTREACHED */
#endif
#undef _
#undef ON
}
コード例 #9
0
ファイル: machdep.c プロジェクト: MarginC/kame
void
intc_intr(int ssr, int spc, int ssp)
{
	struct intc_intrhand *ih;
	int evtcode;
	u_int16_t r;

	evtcode = _reg_read_4(CPU_IS_SH3 ? SH7709_INTEVT2 : SH4_INTEVT);

	ih = EVTCODE_IH(evtcode);
	KDASSERT(ih->ih_func);
	/*
	 * On entry, all interrrupts are disabled,
	 * and exception is enabled for P3 access. (kernel stack is P3,
	 * SH3 may or may not cause TLB miss when access stack.)
	 * Enable higher level interrupt here.
	 */
	r = _reg_read_2(HD6446X_NIRR);

	splx(ih->ih_level);

	if (evtcode == SH_INTEVT_TMU0_TUNI0) {
		struct clockframe cf;
		cf.spc = spc;
		cf.ssr = ssr;
		cf.ssp = ssp;
		(*ih->ih_func)(&cf);
		__dbg_heart_beat(HEART_BEAT_RED);
	} else if (evtcode ==
	    (CPU_IS_SH3 ? SH7709_INTEVT2_IRQ4 : SH_INTEVT_IRL11)) {
		int cause = r & hd6446x_ienable;
		struct hd6446x_intrhand *hh = &hd6446x_intrhand[ffs(cause) - 1];
		if (cause == 0) {
			printf("masked HD6446x interrupt.0x%04x\n", r);
			_reg_write_2(HD6446X_NIRR, 0x0000);
			return;
		}
		/* Enable higher level interrupt*/
		hd6446x_intr_resume(hh->hh_ipl);
		KDASSERT(hh->hh_func != NULL);
		(*hh->hh_func)(hh->hh_arg);
		__dbg_heart_beat(HEART_BEAT_GREEN);
	} else {
		(*ih->ih_func)(ih->ih_arg);
		__dbg_heart_beat(HEART_BEAT_BLUE);
	}
}
コード例 #10
0
ファイル: shpcic.c プロジェクト: lacombar/netbsd-alc
static int
shpcic_match(device_t parent, cfdata_t cf, void *aux)
{
	pcireg_t id;

	if (shpcic_found)
		return (0);

	switch (cpu_product) {
	case CPU_PRODUCT_7751:
	case CPU_PRODUCT_7751R:
		break;

	default:
		return (0);
	}


	id = _reg_read_4(SH4_PCICONF0);

	switch (PCI_VENDOR(id)) {
	case PCI_VENDOR_HITACHI:
		break;

	default:
		return (0);
	}


	switch (PCI_PRODUCT(id)) {
	case PCI_PRODUCT_HITACHI_SH7751: /* FALLTHROUGH */
	case PCI_PRODUCT_HITACHI_SH7751R:
		break;

	default:
		return (0);
	}

	if (_reg_read_2(SH4_BCR2) & BCR2_PORTEN)
		return (0);

	return (1);
}
コード例 #11
0
void
SH3dev::pfc_dump()
{
	DPRINTF((TEXT("<<<Pin Function Controller>>>\n")));
	DPRINTF((TEXT("[control]\n")));
#define	DUMP_PFC_REG(x)							\
	DPRINTF((TEXT("P%SCR :"), #x));					\
	bitdisp(_reg_read_2(SH3_P##x##CR))
	DUMP_PFC_REG(A);
	DUMP_PFC_REG(B);
	DUMP_PFC_REG(C);
	DUMP_PFC_REG(D);
	DUMP_PFC_REG(E);
	DUMP_PFC_REG(F);
	DUMP_PFC_REG(G);
	DUMP_PFC_REG(H);
	DUMP_PFC_REG(J);
	DUMP_PFC_REG(K);
	DUMP_PFC_REG(L);
#undef DUMP_PFC_REG
	DPRINTF((TEXT("SCPCR :")));
	bitdisp(_reg_read_2(SH3_SCPCR));
	DPRINTF((TEXT("\n[data]\n")));
#define	DUMP_IOPORT_REG(x)						\
	DPRINTF((TEXT("P%SDR :"), #x));					\
	bitdisp(_reg_read_1(SH3_P##x##DR))
	DUMP_IOPORT_REG(A);
	DUMP_IOPORT_REG(B);
	DUMP_IOPORT_REG(C);
	DUMP_IOPORT_REG(D);
	DUMP_IOPORT_REG(E);
	DUMP_IOPORT_REG(F);
	DUMP_IOPORT_REG(G);
	DUMP_IOPORT_REG(H);
	DUMP_IOPORT_REG(J);
	DUMP_IOPORT_REG(K);
	DUMP_IOPORT_REG(L);
#undef DUMP_IOPORT_REG
	DPRINTF((TEXT("SCPDR :")));
	bitdisp(_reg_read_1(SH3_SCPDR));
}
コード例 #12
0
ファイル: clock.c プロジェクト: bradla/OpenBSD-Hammer2
void
sh_rtc_get(void *cookie, time_t base, struct clock_ymdhms *dt)
{
	int retry = 8;

	/* disable carry interrupt */
	_reg_bclr_1(SH_(RCR1), SH_RCR1_CIE);

	do {
		uint8_t r = _reg_read_1(SH_(RCR1));
		r &= ~SH_RCR1_CF;
		r |= SH_RCR1_AF; /* don't clear alarm flag */
		_reg_write_1(SH_(RCR1), r);

		if (CPU_IS_SH3)
			dt->dt_year = FROMBCD(_reg_read_1(SH3_RYRCNT));
		else
			dt->dt_year = FROMBCD(_reg_read_2(SH4_RYRCNT) & 0x00ff);

		/* read counter */
#define	RTCGET(x, y)	dt->dt_ ## x = FROMBCD(_reg_read_1(SH_(R ## y ## CNT)))
		RTCGET(mon, MON);
		RTCGET(wday, WK);
		RTCGET(day, DAY);
		RTCGET(hour, HR);
		RTCGET(min, MIN);
		RTCGET(sec, SEC);
#undef RTCGET
	} while ((_reg_read_1(SH_(RCR1)) & SH_RCR1_CF) && --retry > 0);

	if (retry == 0) {
		printf("rtc_gettime: couldn't read RTC register.\n");
		memset(dt, 0, sizeof(*dt));
		return;
	}

	dt->dt_year = (dt->dt_year % 100) + 1900;
	if (dt->dt_year < 1970)
		dt->dt_year += 100;
}
コード例 #13
0
void
SH3dev::tmu_channel_dump(int unit, paddr_t tcor, paddr_t tcnt,
    paddr_t tcr)
{
	uint32_t r32;
	uint16_t r16;

	DPRINTF((TEXT("TMU#%d:"), unit));
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, SH3_TCR_##m, #m)
	/* TCR*/
	r16 = _reg_read_2(tcr);
	DBG_BIT_PRINT(r16, UNF);
	DBG_BIT_PRINT(r16, UNIE);
	DBG_BIT_PRINT(r16, CKEG1);
	DBG_BIT_PRINT(r16, CKEG0);
	DBG_BIT_PRINT(r16, TPSC2);
	DBG_BIT_PRINT(r16, TPSC1);
	DBG_BIT_PRINT(r16, TPSC0);
	/* channel 2 has input capture. */
	if (unit == 2) {
		DBG_BIT_PRINT(r16, ICPF);
		DBG_BIT_PRINT(r16, ICPE1);
		DBG_BIT_PRINT(r16, ICPE0);
	}
#undef DBG_BIT_PRINT
	/* TCNT0  timer counter */
	r32 = _reg_read_4(tcnt);
	DPRINTF((TEXT("\ncnt=0x%08x"), r32));
	/* TCOR0  timer constant register */
	r32 = _reg_read_4(tcor);
	DPRINTF((TEXT(" constant=0x%04x"), r32));

	if (unit == 2)
		DPRINTF((TEXT(" input capture=0x%08x\n"), SH3_TCPR2));
	else
		DPRINTF((TEXT("\n")));
}
コード例 #14
0
int
smap_init(struct ifnet *ifp)
{
	struct smap_softc *sc = ifp->if_softc;
	u_int16_t r16;
	int rc;

	smap_fifo_init(sc);
	emac3_reset(&sc->emac3);
	smap_desc_init(sc);

	_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND | SPD_INTR_TXEND |
	    SPD_INTR_RXDNV);
	emac3_intr_clear();

	r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);
	r16 |=  SPD_INTR_EMAC3 | SPD_INTR_RXEND | SPD_INTR_TXEND |
	    SPD_INTR_RXDNV;
	_reg_write_2(SPD_INTR_ENABLE_REG16, r16);
	emac3_intr_enable();

	emac3_enable();

	/* Program the multicast filter, if necessary. */
	emac3_setmulti(&sc->emac3, &sc->ethercom);

	/* Set current media. */
	if ((rc = mii_mediachg(&sc->emac3.mii)) == ENXIO)
		rc = 0;
	else if (rc != 0)
		return rc;

	ifp->if_flags |= IFF_RUNNING;

	return (0); 
}
コード例 #15
0
void
smap_attach(struct device *parent, struct device *self, void *aux)
{
	struct spd_attach_args *spa = aux;
	struct smap_softc *sc = (void *)self;
	struct emac3_softc *emac3 = &sc->emac3;
	struct ifnet *ifp = &sc->ethercom.ec_if;
	struct mii_data *mii = &emac3->mii;
	void *txbuf, *rxbuf;
	u_int16_t r;

#ifdef SMAP_DEBUG
	__sc = sc;
#endif

	printf(": %s\n", spa->spa_product_name);

	/* SPD EEPROM */
	if (smap_get_eaddr(sc, emac3->eaddr) != 0)
		return;

	printf("%s: Ethernet address %s\n", DEVNAME,
	    ether_sprintf(emac3->eaddr));

	/* disable interrupts */
	r = _reg_read_2(SPD_INTR_ENABLE_REG16);
	r &= ~(SPD_INTR_RXEND | SPD_INTR_TXEND | SPD_INTR_RXDNV |
	    SPD_INTR_EMAC3);
	_reg_write_2(SPD_INTR_ENABLE_REG16, r);
	emac3_intr_disable();

	/* clear pending interrupts */
	_reg_write_2(SPD_INTR_CLEAR_REG16, SPD_INTR_RXEND | SPD_INTR_TXEND |
	    SPD_INTR_RXDNV);
	emac3_intr_clear();

	/* buffer descriptor mode */
	_reg_write_1(SMAP_DESC_MODE_REG8, 0);

	if (smap_fifo_init(sc) != 0)
		return;

	if (emac3_init(&sc->emac3) != 0)
		return;
	emac3_intr_disable();
	emac3_disable();

	smap_desc_init(sc);

	/* allocate temporary buffer */
	txbuf = malloc(ETHER_MAX_LEN - ETHER_CRC_LEN + SMAP_FIFO_ALIGN + 16,
	    M_DEVBUF, M_NOWAIT);
	if (txbuf == NULL) {
		printf("%s: no memory.\n", DEVNAME);		
		return;
	}

	rxbuf = malloc(ETHER_MAX_LEN + SMAP_FIFO_ALIGN + 16,
	    M_DEVBUF, M_NOWAIT);
	if (rxbuf == NULL) {
		printf("%s: no memory.\n", DEVNAME);
		free(txbuf, M_DEVBUF);
		return;
	}

	sc->tx_buf = (u_int32_t *)ROUND16((vaddr_t)txbuf);
	sc->rx_buf = (u_int32_t *)ROUND16((vaddr_t)rxbuf);

	/* 
	 * setup MI layer 
	 */
	strcpy(ifp->if_xname, DEVNAME);
	ifp->if_softc	= sc;
	ifp->if_start	= smap_start;
	ifp->if_ioctl	= smap_ioctl;
	ifp->if_init	= smap_init;
	ifp->if_stop	= smap_stop;
	ifp->if_watchdog= smap_watchdog;
	ifp->if_flags	= IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS |
	    IFF_MULTICAST;
	IFQ_SET_READY(&ifp->if_snd);

	/* ifmedia setup. */
	mii->mii_ifp		= ifp;
	mii->mii_readreg	= emac3_phy_readreg;
	mii->mii_writereg	= emac3_phy_writereg;
	mii->mii_statchg	= emac3_phy_statchg;
	sc->ethercom.ec_mii = mii;
	ifmedia_init(&mii->mii_media, 0, ether_mediachange, ether_mediastatus);
	mii_attach(&emac3->dev, mii, 0xffffffff, MII_PHY_ANY,
	    MII_OFFSET_ANY, 0);
	    
	/* Choose a default media. */
	if (LIST_FIRST(&mii->mii_phys) == NULL) {
		ifmedia_add(&mii->mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
		ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_NONE);
	} else {
		ifmedia_set(&mii->mii_media, IFM_ETHER|IFM_AUTO);
	}

	if_attach(ifp);
	ether_ifattach(ifp, emac3->eaddr);
	
	spd_intr_establish(SPD_NIC, smap_intr, sc);

#if NRND > 0
	rnd_attach_source(&sc->rnd_source, DEVNAME,
	    RND_TYPE_NET, RND_FLAG_DEFAULT);
#endif
}
コード例 #16
0
ファイル: shpcic.c プロジェクト: lacombar/netbsd-alc
static void
shpcic_attach(device_t parent, device_t self, void *aux)
{
	struct pcibus_attach_args pba;
#ifdef PCI_NETBSD_CONFIGURE
	struct extent *ioext, *memext;
#endif
	pcireg_t id, class;
	char devinfo[256];

	shpcic_found = 1;

	aprint_naive("\n");

	id = _reg_read_4(SH4_PCICONF0);
	class = _reg_read_4(SH4_PCICONF2);
	pci_devinfo(id, class, 1, devinfo, sizeof(devinfo));
	aprint_normal(": %s\n", devinfo);

	/* allow PCIC request */
	_reg_write_4(SH4_BCR1, _reg_read_4(SH4_BCR1) | BCR1_BREQEN);

	/* Initialize PCIC */
	_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_RSTCTL);
	delay(10 * 1000);
	_reg_write_4(SH4_PCICR, PCICR_BASE);

	/* Class: Host-Bridge */
	_reg_write_4(SH4_PCICONF2,
	    PCI_CLASS_CODE(PCI_CLASS_BRIDGE, PCI_SUBCLASS_BRIDGE_HOST, 0x00));

#if !defined(DONT_INIT_PCIBSC)
#if defined(PCIBCR_BCR1_VAL)
	_reg_write_4(SH4_PCIBCR1, PCIBCR_BCR1_VAL);
#else
	_reg_write_4(SH4_PCIBCR1, _reg_read_4(SH4_BCR1) | BCR1_MASTER);
#endif
#if defined(PCIBCR_BCR2_VAL)
	_reg_write_4(SH4_PCIBCR2, PCIBCR_BCR2_VAL);
#else
	_reg_write_4(SH4_PCIBCR2, _reg_read_2(SH4_BCR2));
#endif
#if defined(SH4) && defined(SH7751R)
	if (cpu_product == CPU_PRODUCT_7751R) {
#if defined(PCIBCR_BCR3_VAL)
		_reg_write_4(SH4_PCIBCR3, PCIBCR_BCR3_VAL);
#else
		_reg_write_4(SH4_PCIBCR3, _reg_read_2(SH4_BCR3));
#endif
	}
#endif	/* SH4 && SH7751R && PCIBCR_BCR3_VAL */
#if defined(PCIBCR_WCR1_VAL)
	_reg_write_4(SH4_PCIWCR1, PCIBCR_WCR1_VAL);
#else
	_reg_write_4(SH4_PCIWCR1, _reg_read_4(SH4_WCR1));
#endif
#if defined(PCIBCR_WCR2_VAL)
	_reg_write_4(SH4_PCIWCR2, PCIBCR_WCR2_VAL);
#else
	_reg_write_4(SH4_PCIWCR2, _reg_read_4(SH4_WCR2));
#endif
#if defined(PCIBCR_WCR3_VAL)
	_reg_write_4(SH4_PCIWCR3, PCIBCR_WCR3_VAL);
#else
	_reg_write_4(SH4_PCIWCR3, _reg_read_4(SH4_WCR3));
#endif
#if defined(PCIBCR_MCR_VAL)
	_reg_write_4(SH4_PCIMCR, PCIBCR_MCR_VAL);
#else
	_reg_write_4(SH4_PCIMCR, _reg_read_4(SH4_MCR));
#endif
#endif	/* !DONT_INIT_PCIBSC */

	/* set PCI I/O, memory base address */
	_reg_write_4(SH4_PCIIOBR, SH4_PCIC_IO);
	_reg_write_4(SH4_PCIMBR, SH4_PCIC_MEM);

	/* set PCI local address 0 */
	_reg_write_4(SH4_PCILSR0, (64 - 1) << 20);
	_reg_write_4(SH4_PCILAR0, 0xac000000);
	_reg_write_4(SH4_PCICONF5, 0xac000000);

	/* set PCI local address 1 */
	_reg_write_4(SH4_PCILSR1, (64 - 1) << 20);
	_reg_write_4(SH4_PCILAR1, 0xac000000);
	_reg_write_4(SH4_PCICONF6, 0x8c000000);

	/* Enable I/O, memory, bus-master */
	_reg_write_4(SH4_PCICONF1, PCI_COMMAND_IO_ENABLE
	                           | PCI_COMMAND_MEM_ENABLE
	                           | PCI_COMMAND_MASTER_ENABLE
	                           | PCI_COMMAND_STEPPING_ENABLE
				   | PCI_STATUS_DEVSEL_MEDIUM);

	/* Initialize done. */
	_reg_write_4(SH4_PCICR, PCICR_BASE | PCICR_CFINIT);

	/* set PCI controller interrupt priority */
	intpri_intr_priority(SH4_INTEVT_PCIERR, shpcic_intr_priority[0]);
	intpri_intr_priority(SH4_INTEVT_PCISERR, shpcic_intr_priority[1]);

	/* PCI bus */
#ifdef PCI_NETBSD_CONFIGURE
	ioext  = extent_create("pciio",
	    SH4_PCIC_IO, SH4_PCIC_IO + SH4_PCIC_IO_SIZE - 1,
	    M_DEVBUF, NULL, 0, EX_NOWAIT);
	memext = extent_create("pcimem",
	    SH4_PCIC_MEM, SH4_PCIC_MEM + SH4_PCIC_MEM_SIZE - 1,
	    M_DEVBUF, NULL, 0, EX_NOWAIT);

	pci_configure_bus(NULL, ioext, memext, NULL, 0, sh_cache_line_size);

	extent_destroy(ioext);
	extent_destroy(memext);
#endif

	/* PCI bus */
	memset(&pba, 0, sizeof(pba));
	pba.pba_iot = shpcic_get_bus_io_tag();
	pba.pba_memt = shpcic_get_bus_mem_tag();
	pba.pba_dmat = shpcic_get_bus_dma_tag();
	pba.pba_dmat64 = NULL;
	pba.pba_pc = NULL;
	pba.pba_bus = 0;
	pba.pba_bridgetag = NULL;
	pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
	config_found(self, &pba, NULL);
}
コード例 #17
0
void
smap_start(struct ifnet *ifp)
{
	struct smap_softc *sc = ifp->if_softc;
	struct smap_desc *d;
	struct mbuf *m0, *m;
	u_int8_t *p, *q;
	u_int32_t *r;
	int i, sz, pktsz;
	u_int16_t fifop;
	u_int16_t r16;

	KDASSERT(ifp->if_flags & IFF_RUNNING);
	FUNC_ENTER();

	while (1) {
		IFQ_POLL(&ifp->if_snd, m0);
		if (m0 == NULL)
			goto end;

		pktsz = m0->m_pkthdr.len;
		KDASSERT(pktsz <= ETHER_MAX_LEN - ETHER_CRC_LEN);
		sz = ROUND4(pktsz);

		if (sz > sc->tx_buf_freesize ||
		    sc->tx_desc_cnt >= SMAP_DESC_MAX ||
		    emac3_tx_done() != 0) {
			ifp->if_flags |= IFF_OACTIVE;
			goto end;
		}

		IFQ_DEQUEUE(&ifp->if_snd, m0);
		KDASSERT(m0 != NULL);
		if (ifp->if_bpf)
			bpf_mtap(ifp->if_bpf, m0);

		p = (u_int8_t *)sc->tx_buf;
		q = p + sz;
		/* copy to temporary buffer area */
		for (m = m0; m != 0; m = m->m_next) {
			memcpy(p, mtod(m, void *), m->m_len);
			p += m->m_len;
		}
		m_freem(m0);

		/* zero padding area */
		for (; p < q; p++)
			*p = 0;

		/* put to FIFO */
		fifop = sc->tx_fifo_ptr;
		KDASSERT((fifop & 3) == 0);
		_reg_write_2(SMAP_TXFIFO_PTR_REG16, fifop);
		sc->tx_fifo_ptr = (fifop + sz) & 0xfff;

		r = sc->tx_buf;
		for (i = 0; i < sz; i += sizeof(u_int32_t))
			*(volatile u_int32_t *)SMAP_TXFIFO_DATA_REG = *r++;
		_wbflush();

		/* put FIFO to EMAC3 */
		d = &sc->tx_desc[sc->tx_start_index];
		KDASSERT((d->stat & SMAP_TXDESC_READY) == 0);

		d->sz = pktsz;
		d->ptr = fifop + SMAP_TXBUF_BASE;
		d->stat = SMAP_TXDESC_READY | SMAP_TXDESC_GENFCS |
		    SMAP_TXDESC_GENPAD;
		_wbflush();

		sc->tx_buf_freesize -= sz;
		sc->tx_desc_cnt++;
		sc->tx_start_index = (sc->tx_start_index + 1) & 0x3f;
		_reg_write_1(SMAP_TXFIFO_FRAME_INC_REG8, 1);

		emac3_tx_kick();
		r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);
		if ((r16 & SPD_INTR_TXDNV) == 0) {
			r16 |= SPD_INTR_TXDNV;
			_reg_write_2(SPD_INTR_ENABLE_REG16, r16);
		}
	}
 end:
	/* set watchdog timer */
	ifp->if_timer = 5;

	FUNC_EXIT();
}
コード例 #18
0
void
smap_rxeof(void *arg)
{
	struct smap_softc *sc = arg;
	struct smap_desc *d;
	struct ifnet *ifp = &sc->ethercom.ec_if;
	struct mbuf *m;
	u_int16_t r16, stat;
	u_int32_t *p;
	int i, j, sz, rxsz, cnt;

	FUNC_ENTER();

	i = sc->rx_done_index;

	for (cnt = 0;; cnt++, i = (i + 1) & 0x3f) {
		m = NULL;
		d = &sc->rx_desc[i];
		stat = d->stat;

		if ((stat & SMAP_RXDESC_EMPTY) != 0) {
			break;
		} else if (stat & 0x7fff) {
			ifp->if_ierrors++;
			goto next_packet;
		}

		sz = d->sz;
		rxsz = ROUND4(sz);

		KDASSERT(sz >= ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN);
		KDASSERT(sz <= ETHER_MAX_LEN);

		/* load data from FIFO */
		_reg_write_2(SMAP_RXFIFO_PTR_REG16, d->ptr & 0x3ffc);
		p = sc->rx_buf;
		for (j = 0; j < rxsz; j += sizeof(u_int32_t)) {
			*p++ = _reg_read_4(SMAP_RXFIFO_DATA_REG);
		}

		/* put to mbuf */
		MGETHDR(m, M_DONTWAIT, MT_DATA);
		if (m == NULL) {
			printf("%s: unable to allocate Rx mbuf\n", DEVNAME);
			ifp->if_ierrors++;
			goto next_packet;
		}

		if (sz > (MHLEN - 2)) {
			MCLGET(m, M_DONTWAIT);
			if ((m->m_flags & M_EXT) == 0) {
				printf("%s: unable to allocate Rx cluster\n",
				    DEVNAME);
				m_freem(m);
				m = NULL;
				ifp->if_ierrors++;
				goto next_packet;
			}
		}

		m->m_data += 2; /* for alignment */
		m->m_pkthdr.rcvif = ifp;
		m->m_pkthdr.len = m->m_len = sz;
		memcpy(mtod(m, void *), (void *)sc->rx_buf, sz);

	next_packet:
		ifp->if_ipackets++;

		_reg_write_1(SMAP_RXFIFO_FRAME_DEC_REG8, 1);

		/* free descriptor */
		d->sz	= 0;
		d->ptr	= 0;
		d->stat	= SMAP_RXDESC_EMPTY;
		_wbflush();
		
		if (m != NULL) {
			if (ifp->if_bpf)
				bpf_mtap(ifp->if_bpf, m);
			(*ifp->if_input)(ifp, m);
		}
	}
	sc->rx_done_index = i;

	r16 = _reg_read_2(SPD_INTR_ENABLE_REG16);
	if (((r16 & SPD_INTR_RXDNV) == 0) && cnt > 0) {
		r16  |= SPD_INTR_RXDNV;
		_reg_write_2(SPD_INTR_ENABLE_REG16, r16);
	}

	FUNC_EXIT();
}
コード例 #19
0
void
SH3dev::hd64461_dump(platid_t &platform)
{
	uint16_t r16;
	uint8_t r8;

#define	MATCH(p)						\
	platid_match(&platform, &platid_mask_MACH_##p)

	DPRINTF((TEXT("<<<HD64461>>>\n")));
	if (!MATCH(HP_LX) &&
	    !MATCH(HP_JORNADA_6XX) &&
	    !MATCH(HITACHI_PERSONA_HPW230JC)) {
		DPRINTF((TEXT("don't exist.")));
		return;
	}

#if 0
	DPRINTF((TEXT("frame buffer test start\n")));
	uint8_t *fb = reinterpret_cast<uint8_t *>(HD64461_FBBASE);

	for (int i = 0; i < 320 * 240 * 2 / 8; i++)
		*fb++ = 0xff;
	DPRINTF((TEXT("frame buffer test end\n")));
#endif
	// System
	DPRINTF((TEXT("STBCR (System Control Register)\n")));
	r16 = _reg_read_2(HD64461_SYSSTBCR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_SYSSTBCR_##m, #m)
	DBG_BIT_PRINT(r16, CKIO_STBY);
	DBG_BIT_PRINT(r16, SAFECKE_IST);
	DBG_BIT_PRINT(r16, SLCKE_IST);
	DBG_BIT_PRINT(r16, SAFECKE_OST);
	DBG_BIT_PRINT(r16, SLCKE_OST);
	DBG_BIT_PRINT(r16, SMIAST);
	DBG_BIT_PRINT(r16, SLCDST);
	DBG_BIT_PRINT(r16, SPC0ST);
	DBG_BIT_PRINT(r16, SPC1ST);
	DBG_BIT_PRINT(r16, SAFEST);
	DBG_BIT_PRINT(r16, STM0ST);
	DBG_BIT_PRINT(r16, STM1ST);
	DBG_BIT_PRINT(r16, SIRST);
	DBG_BIT_PRINT(r16, SURTSD);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("SYSCR (System Configuration Register)\n")));
	r16 = _reg_read_2(HD64461_SYSSYSCR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_SYSSYSCR_##m, #m)
	DBG_BIT_PRINT(r16, SCPU_BUS_IGAT);
	DBG_BIT_PRINT(r16, SPTA_IR);
	DBG_BIT_PRINT(r16, SPTA_TM);
	DBG_BIT_PRINT(r16, SPTB_UR);
	DBG_BIT_PRINT(r16, WAIT_CTL_SEL);
	DBG_BIT_PRINT(r16, SMODE1);
	DBG_BIT_PRINT(r16, SMODE0);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("SCPUCR (CPU Data Bus Control Register)\n")));
	r16 = _reg_read_2(HD64461_SYSSCPUCR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_SYSSCPUCR_##m, #m)
	DBG_BIT_PRINT(r16, SPDSTOF);
	DBG_BIT_PRINT(r16, SPDSTIG);
	DBG_BIT_PRINT(r16, SPCSTOF);
	DBG_BIT_PRINT(r16, SPCSTIG);
	DBG_BIT_PRINT(r16, SPBSTOF);
	DBG_BIT_PRINT(r16, SPBSTIG);
	DBG_BIT_PRINT(r16, SPASTOF);
	DBG_BIT_PRINT(r16, SPASTIG);
	DBG_BIT_PRINT(r16, SLCDSTIG);
	DBG_BIT_PRINT(r16, SCPU_CS56_EP);
	DBG_BIT_PRINT(r16, SCPU_CMD_EP);
	DBG_BIT_PRINT(r16, SCPU_ADDR_EP);
	DBG_BIT_PRINT(r16, SCPDPU);
	DBG_BIT_PRINT(r16, SCPU_A2319_EP);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("\n")));

	// INTC
	DPRINTF((TEXT("NIRR (Interrupt Request Register)\n")));
	r16 = _reg_read_2(HD64461_INTCNIRR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_INTCNIRR_##m, #m)
	DBG_BIT_PRINT(r16, PCC0R);
	DBG_BIT_PRINT(r16, PCC1R);
	DBG_BIT_PRINT(r16, AFER);
	DBG_BIT_PRINT(r16, GPIOR);
	DBG_BIT_PRINT(r16, TMU0R);
	DBG_BIT_PRINT(r16, TMU1R);
	DBG_BIT_PRINT(r16, IRDAR);
	DBG_BIT_PRINT(r16, UARTR);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("NIMR (Interrupt Mask Register)\n")));
	r16 = _reg_read_2(HD64461_INTCNIMR_REG16);
	bitdisp(r16);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_INTCNIMR_##m, #m)
	DBG_BIT_PRINT(r16, PCC0M);
	DBG_BIT_PRINT(r16, PCC1M);
	DBG_BIT_PRINT(r16, AFEM);
	DBG_BIT_PRINT(r16, GPIOM);
	DBG_BIT_PRINT(r16, TMU0M);
	DBG_BIT_PRINT(r16, TMU1M);
	DBG_BIT_PRINT(r16, IRDAM);
	DBG_BIT_PRINT(r16, UARTM);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("\n")));

	// PCMCIA
	// PCC0
	DPRINTF((TEXT("[PCC0 memory and I/O card (SH3 Area 6)]\n")));
	DPRINTF((TEXT("PCC0 Interface Status Register\n")));
	r8 = _reg_read_1(HD64461_PCC0ISR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0ISR_##m, #m)
	DBG_BIT_PRINT(r8, P0READY);
	DBG_BIT_PRINT(r8, P0MWP);
	DBG_BIT_PRINT(r8, P0VS2);
	DBG_BIT_PRINT(r8, P0VS1);
	DBG_BIT_PRINT(r8, P0CD2);
	DBG_BIT_PRINT(r8, P0CD1);
	DBG_BIT_PRINT(r8, P0BVD2);
	DBG_BIT_PRINT(r8, P0BVD1);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC0 General Control Register\n")));
	r8 = _reg_read_1(HD64461_PCC0GCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0GCR_##m, #m)
	DBG_BIT_PRINT(r8, P0DRVE);
	DBG_BIT_PRINT(r8, P0PCCR);
	DBG_BIT_PRINT(r8, P0PCCT);
	DBG_BIT_PRINT(r8, P0VCC0);
	DBG_BIT_PRINT(r8, P0MMOD);
	DBG_BIT_PRINT(r8, P0PA25);
	DBG_BIT_PRINT(r8, P0PA24);
	DBG_BIT_PRINT(r8, P0REG);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC0 Card Status Change Register\n")));
	r8 = _reg_read_1(HD64461_PCC0CSCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0CSCR_##m, #m)
	DBG_BIT_PRINT(r8, P0SCDI);
	DBG_BIT_PRINT(r8, P0IREQ);
	DBG_BIT_PRINT(r8, P0SC);
	DBG_BIT_PRINT(r8, P0CDC);
	DBG_BIT_PRINT(r8, P0RC);
	DBG_BIT_PRINT(r8, P0BW);
	DBG_BIT_PRINT(r8, P0BD);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC0 Card Status Change Interrupt Enable Register\n")));
	r8 = _reg_read_1(HD64461_PCC0CSCIER_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0CSCIER_##m, #m)
	DBG_BIT_PRINT(r8, P0CRE);
	DBG_BIT_PRINT(r8, P0SCE);
	DBG_BIT_PRINT(r8, P0CDE);
	DBG_BIT_PRINT(r8, P0RE);
	DBG_BIT_PRINT(r8, P0BWE);
	DBG_BIT_PRINT(r8, P0BDE);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\ninterrupt type: ")));
	switch (r8 & HD64461_PCC0CSCIER_P0IREQE_MASK) {
	case HD64461_PCC0CSCIER_P0IREQE_NONE:
		DPRINTF((TEXT("none\n")));
		break;
	case HD64461_PCC0CSCIER_P0IREQE_LEVEL:
		DPRINTF((TEXT("level\n")));
		break;
	case HD64461_PCC0CSCIER_P0IREQE_FEDGE:
		DPRINTF((TEXT("falling edge\n")));
		break;
	case HD64461_PCC0CSCIER_P0IREQE_REDGE:
		DPRINTF((TEXT("rising edge\n")));
		break;
	}

	DPRINTF((TEXT("PCC0 Software Control Register\n")));
	r8 = _reg_read_1(HD64461_PCC0SCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC0SCR_##m, #m)
	DBG_BIT_PRINT(r8, P0VCC1);
	DBG_BIT_PRINT(r8, P0SWP);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	// PCC1
	DPRINTF((TEXT("[PCC1 memory card only (SH3 Area 5)]\n")));
	DPRINTF((TEXT("PCC1 Interface Status Register\n")));
	r8 = _reg_read_1(HD64461_PCC1ISR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1ISR_##m, #m)
	DBG_BIT_PRINT(r8, P1READY);
	DBG_BIT_PRINT(r8, P1MWP);
	DBG_BIT_PRINT(r8, P1VS2);
	DBG_BIT_PRINT(r8, P1VS1);
	DBG_BIT_PRINT(r8, P1CD2);
	DBG_BIT_PRINT(r8, P1CD1);
	DBG_BIT_PRINT(r8, P1BVD2);
	DBG_BIT_PRINT(r8, P1BVD1);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 General Contorol Register\n")));
	r8 = _reg_read_1(HD64461_PCC1GCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1GCR_##m, #m)
	DBG_BIT_PRINT(r8, P1DRVE);
	DBG_BIT_PRINT(r8, P1PCCR);
	DBG_BIT_PRINT(r8, P1VCC0);
	DBG_BIT_PRINT(r8, P1MMOD);
	DBG_BIT_PRINT(r8, P1PA25);
	DBG_BIT_PRINT(r8, P1PA24);
	DBG_BIT_PRINT(r8, P1REG);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 Card Status Change Register\n")));
	r8 = _reg_read_1(HD64461_PCC1CSCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1CSCR_##m, #m)
	DBG_BIT_PRINT(r8, P1SCDI);
	DBG_BIT_PRINT(r8, P1CDC);
	DBG_BIT_PRINT(r8, P1RC);
	DBG_BIT_PRINT(r8, P1BW);
	DBG_BIT_PRINT(r8, P1BD);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 Card Status Change Interrupt Enable Register\n")));
	r8 = _reg_read_1(HD64461_PCC1CSCIER_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1CSCIER_##m, #m)
	DBG_BIT_PRINT(r8, P1CRE);
	DBG_BIT_PRINT(r8, P1CDE);
	DBG_BIT_PRINT(r8, P1RE);
	DBG_BIT_PRINT(r8, P1BWE);
	DBG_BIT_PRINT(r8, P1BDE);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 Software Control Register\n")));
	r8 = _reg_read_1(HD64461_PCC1SCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCC1SCR_##m, #m)
	DBG_BIT_PRINT(r8, P1VCC1);
	DBG_BIT_PRINT(r8, P1SWP);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	// General Control
	DPRINTF((TEXT("[General Control]\n")));
	DPRINTF((TEXT("PCC0 Output pins Control Register\n")));
	r8 = _reg_read_1(HD64461_PCCP0OCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCCP0OCR_##m, #m)
	DBG_BIT_PRINT(r8, P0DEPLUP);
	DBG_BIT_PRINT(r8, P0AEPLUP);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PCC1 Output pins Control Register\n")));
	r8 = _reg_read_1(HD64461_PCCP1OCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCCP1OCR_##m, #m)
	DBG_BIT_PRINT(r8, P1RST8MA);
	DBG_BIT_PRINT(r8, P1RST4MA);
	DBG_BIT_PRINT(r8, P1RAS8MA);
	DBG_BIT_PRINT(r8, P1RAS4MA);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	DPRINTF((TEXT("PC Card General Control Register\n")));
	r8 = _reg_read_1(HD64461_PCCPGCR_REG8);
	bitdisp(r8);
#define	DBG_BIT_PRINT(r, m)	_dbg_bit_print(r, HD64461_PCCPGCR_##m, #m)
	DBG_BIT_PRINT(r8, PSSDIR);
	DBG_BIT_PRINT(r8, PSSRDWR);
#undef DBG_BIT_PRINT
	DPRINTF((TEXT("\n")));

	// GPIO
#define	GPIO_DUMP(x)							\
	bitdisp(_reg_read_2(HD64461_GPA##x##R_REG16));			\
	bitdisp(_reg_read_2(HD64461_GPB##x##R_REG16));			\
	bitdisp(_reg_read_2(HD64461_GPC##x##R_REG16));			\
	bitdisp(_reg_read_2(HD64461_GPD##x##R_REG16))

	DPRINTF((TEXT("GPIO Port Control Register\n")));
	GPIO_DUMP(C);
	DPRINTF((TEXT("GPIO Port Data Register\n")));
	GPIO_DUMP(D);
	DPRINTF((TEXT("GPIO Port Interrupt Control Register\n")));
	GPIO_DUMP(IC);
	DPRINTF((TEXT("GPIO Port Interrupt Status  Register\n")));
	GPIO_DUMP(IS);
}