/** Initializes the XOSC32K crystal failure detector, and starts it. * * \param[in] ok_callback Callback function to run upon XOSC32K operational * \param[in] fail_callback Callback function to run upon XOSC32K failure */ static void init_xosc32k_fail_detector( const tc_callback_t ok_callback, const tc_callback_t fail_callback) { /* TC pairs share the same clock, ensure reference and crystal timers use * different clocks */ Assert(Abs(_tc_get_inst_index(CONF_TC_OSC32K) - _tc_get_inst_index(CONF_TC_XOSC32K)) >= 2); /* The crystal detection cycle count must be less than the reference cycle * count, so that the reference timer is periodically reset before expiry */ Assert(CRYSTAL_RESET_CYCLES < CRYSTAL_FAIL_CYCLES); /* Must use different clock generators for the crystal and reference, must * not be CPU generator 0 */ Assert(GCLK_GENERATOR_XOSC32K != GCLK_GENERATOR_OSC32K); Assert(GCLK_GENERATOR_XOSC32K != GCLK_GENERATOR_0); Assert(GCLK_GENERATOR_OSC32K != GCLK_GENERATOR_0); /* Configure and enable the XOSC32K GCLK generator */ struct system_gclk_gen_config xosc32k_gen_conf; system_gclk_gen_get_config_defaults(&xosc32k_gen_conf); xosc32k_gen_conf.source_clock = SYSTEM_CLOCK_SOURCE_XOSC32K; system_gclk_gen_set_config(GCLK_GENERATOR_XOSC32K, &xosc32k_gen_conf); system_gclk_gen_enable(GCLK_GENERATOR_XOSC32K); /* Configure and enable the reference clock GCLK generator */ struct system_gclk_gen_config ref_gen_conf; system_gclk_gen_get_config_defaults(&ref_gen_conf); ref_gen_conf.source_clock = SYSTEM_CLOCK_SOURCE_OSC32K; system_gclk_gen_set_config(GCLK_GENERATOR_OSC32K, &ref_gen_conf); system_gclk_gen_enable(GCLK_GENERATOR_OSC32K); /* Set up crystal counter - when target count elapses, trigger event */ struct tc_config tc_xosc32k_conf; tc_get_config_defaults(&tc_xosc32k_conf); tc_xosc32k_conf.clock_source = GCLK_GENERATOR_XOSC32K; tc_xosc32k_conf.counter_16_bit.compare_capture_channel[0] = CRYSTAL_RESET_CYCLES; tc_xosc32k_conf.wave_generation = TC_WAVE_GENERATION_MATCH_FREQ; tc_init(&tc_xosc32k, CONF_TC_XOSC32K, &tc_xosc32k_conf); /* Set up reference counter - when event received, restart */ struct tc_config tc_osc32k_conf; tc_get_config_defaults(&tc_osc32k_conf); tc_osc32k_conf.clock_source = GCLK_GENERATOR_OSC32K; tc_osc32k_conf.counter_16_bit.compare_capture_channel[0] = CRYSTAL_FAIL_CYCLES; tc_osc32k_conf.wave_generation = TC_WAVE_GENERATION_MATCH_FREQ; tc_init(&tc_osc32k, CONF_TC_OSC32K, &tc_osc32k_conf); /* Configure event channel and link it to the xosc32k counter */ struct events_config config; struct events_resource event; events_get_config_defaults(&config); config.edge_detect = EVENTS_EDGE_DETECT_NONE; config.generator = CONF_EVENT_GENERATOR_ID; config.path = EVENTS_PATH_ASYNCHRONOUS; events_allocate(&event, &config); /* Configure event user and link it to the osc32k counter */ events_attach_user(&event, CONF_EVENT_USED_ID); /* Enable event generation for crystal counter */ struct tc_events tc_xosc32k_events = { .generate_event_on_overflow = true }; tc_enable_events(&tc_xosc32k, &tc_xosc32k_events); /* Enable event reception for reference counter */ struct tc_events tc_osc32k_events = { .on_event_perform_action = true }; tc_osc32k_events.event_action = TC_EVENT_ACTION_RETRIGGER; tc_enable_events(&tc_osc32k, &tc_osc32k_events); /* Enable overflow callback for the crystal counter - if crystal count * has been reached, crystal is operational */ tc_register_callback(&tc_xosc32k, ok_callback, TC_CALLBACK_CC_CHANNEL0); tc_enable_callback(&tc_xosc32k, TC_CALLBACK_CC_CHANNEL0); /* Enable compare callback for the reference counter - if reference count * has been reached, crystal has failed */ tc_register_callback(&tc_osc32k, fail_callback, TC_CALLBACK_CC_CHANNEL0); tc_enable_callback(&tc_osc32k, TC_CALLBACK_CC_CHANNEL0); /* Start both crystal and reference counters */ tc_enable(&tc_xosc32k); tc_enable(&tc_osc32k); } /** Main application entry point. */ int main(void) { system_init(); system_flash_set_waitstates(2); init_osc32k(); init_xosc32k(); init_xosc32k_fail_detector( xosc32k_ok_callback, xosc32k_fail_callback); #if ENABLE_CPU_CLOCK_OUT == true /* Configure a GPIO pin as the CPU clock output */ struct system_pinmux_config clk_out_pin; system_pinmux_get_config_defaults(&clk_out_pin); clk_out_pin.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; clk_out_pin.mux_position = CONF_CLOCK_PIN_MUX; system_pinmux_pin_set_config(CONF_CLOCK_PIN_OUT, &clk_out_pin); #endif for (;;) { static bool old_run_osc = true; bool new_run_osc = (port_pin_get_input_level(BUTTON_0_PIN) == BUTTON_0_INACTIVE); /* Check if the XOSC32K needs to be started or stopped when the board * button is pressed or released */ if (new_run_osc != old_run_osc) { if (new_run_osc) { system_clock_source_enable(SYSTEM_CLOCK_SOURCE_XOSC32K); while(!system_clock_source_is_ready( SYSTEM_CLOCK_SOURCE_XOSC32K)); } else { system_clock_source_disable(SYSTEM_CLOCK_SOURCE_XOSC32K); } old_run_osc = new_run_osc; } } }
/** * \brief Initializes a hardware TC module instance. * * Enables the clock and initializes the TC module, based on the given * configuration values. * * \param[in,out] module_inst Pointer to the software module instance struct * \param[in] hw Pointer to the TC hardware module * \param[in] config Pointer to the TC configuration options struct * * \return Status of the initialization procedure. * * \retval STATUS_OK The module was initialized successfully * \retval STATUS_BUSY Hardware module was busy when the * initialization procedure was attempted * \retval STATUS_INVALID_ARG An invalid configuration option or argument * was supplied * \retval STATUS_ERR_DENIED Hardware module was already enabled, or the * hardware module is configured in 32-bit * slave mode */ enum status_code tc_init( struct tc_module *const module_inst, Tc *const hw, const struct tc_config *const config) { /* Sanity check arguments */ Assert(hw); Assert(module_inst); Assert(config); /* Temporary variable to hold all updates to the CTRLA * register before they are written to it */ uint16_t ctrla_tmp = 0; /* Temporary variable to hold all updates to the CTRLBSET * register before they are written to it */ uint8_t ctrlbset_tmp = 0; /* Temporary variable to hold all updates to the CTRLC * register before they are written to it */ uint8_t ctrlc_tmp = 0; /* Temporary variable to hold TC instance number */ uint8_t instance = _tc_get_inst_index(hw); /* Array of GLCK ID for different TC instances */ uint8_t inst_gclk_id[] = TC_INST_GCLK_ID; /* Array of PM APBC mask bit position for different TC instances */ uint16_t inst_pm_apbmask[] = TC_INST_PM_APBCMASK; struct system_pinmux_config pin_config; struct system_gclk_chan_config gclk_chan_config; #if TC_ASYNC == true /* Initialize parameters */ for (uint8_t i = 0; i < TC_CALLBACK_N; i++) { module_inst->callback[i] = NULL; } module_inst->register_callback_mask = 0x00; module_inst->enable_callback_mask = 0x00; /* Register this instance for callbacks*/ _tc_instances[instance] = module_inst; #endif /* Associate the given device instance with the hardware module */ module_inst->hw = hw; #if SAMD10 || SAMD11 /* Check if even numbered TC modules are being configured in 32-bit * counter size. Only odd numbered counters are allowed to be * configured in 32-bit counter size. */ if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && !((instance + TC_INSTANCE_OFFSET) & 0x01)) { Assert(false); return STATUS_ERR_INVALID_ARG; } #else /* Check if odd numbered TC modules are being configured in 32-bit * counter size. Only even numbered counters are allowed to be * configured in 32-bit counter size. */ if ((config->counter_size == TC_COUNTER_SIZE_32BIT) && ((instance + TC_INSTANCE_OFFSET) & 0x01)) { Assert(false); return STATUS_ERR_INVALID_ARG; } #endif /* Make the counter size variable in the module_inst struct reflect * the counter size in the module */ module_inst->counter_size = config->counter_size; if (hw->COUNT8.CTRLA.reg & TC_CTRLA_SWRST) { /* We are in the middle of a reset. Abort. */ return STATUS_BUSY; } if (hw->COUNT8.STATUS.reg & TC_STATUS_SLAVE) { /* Module is used as a slave */ return STATUS_ERR_DENIED; } if (hw->COUNT8.CTRLA.reg & TC_CTRLA_ENABLE) { /* Module must be disabled before initialization. Abort. */ return STATUS_ERR_DENIED; } /* Set up the TC PWM out pin for channel 0 */ if (config->pwm_channel[0].enabled) { system_pinmux_get_config_defaults(&pin_config); pin_config.mux_position = config->pwm_channel[0].pin_mux; pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; system_pinmux_pin_set_config( config->pwm_channel[0].pin_out, &pin_config); } /* Set up the TC PWM out pin for channel 1 */ if (config->pwm_channel[1].enabled) { system_pinmux_get_config_defaults(&pin_config); pin_config.mux_position = config->pwm_channel[1].pin_mux; pin_config.direction = SYSTEM_PINMUX_PIN_DIR_OUTPUT; system_pinmux_pin_set_config( config->pwm_channel[1].pin_out, &pin_config); } /* Enable the user interface clock in the PM */ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, inst_pm_apbmask[instance]); /* Enable the slave counter if counter_size is 32-bit */ if ((config->counter_size == TC_COUNTER_SIZE_32BIT)) { /* Enable the user interface clock in the PM */ system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, inst_pm_apbmask[instance + 1]); } /* Setup clock for module */ system_gclk_chan_get_config_defaults(&gclk_chan_config); gclk_chan_config.source_generator = config->clock_source; system_gclk_chan_set_config(inst_gclk_id[instance], &gclk_chan_config); system_gclk_chan_enable(inst_gclk_id[instance]); /* Set ctrla register */ ctrla_tmp = (uint32_t)config->counter_size | (uint32_t)config->wave_generation | (uint32_t)config->reload_action | (uint32_t)config->clock_prescaler; if (config->run_in_standby) { ctrla_tmp |= TC_CTRLA_RUNSTDBY; } /* Write configuration to register */ while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT8.CTRLA.reg = ctrla_tmp; /* Set ctrlb register */ if (config->oneshot) { ctrlbset_tmp = TC_CTRLBSET_ONESHOT; } if (config->count_direction) { ctrlbset_tmp |= TC_CTRLBSET_DIR; } /* Clear old ctrlb configuration */ while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT8.CTRLBCLR.reg = 0xFF; /* Check if we actually need to go into a wait state. */ if (ctrlbset_tmp) { while (tc_is_syncing(module_inst)) { /* Wait for sync */ } /* Write configuration to register */ hw->COUNT8.CTRLBSET.reg = ctrlbset_tmp; } /* Set ctrlc register*/ ctrlc_tmp = config->waveform_invert_output; for (uint8_t i = 0; i < NUMBER_OF_COMPARE_CAPTURE_CHANNELS; i++) { if (config->enable_capture_on_channel[i] == true) { ctrlc_tmp |= (TC_CTRLC_CPTEN(1) << i); } } /* Write configuration to register */ while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT8.CTRLC.reg = ctrlc_tmp; /* Write configuration to register */ while (tc_is_syncing(module_inst)) { /* Wait for sync */ } /* Switch for TC counter size */ switch (module_inst->counter_size) { case TC_COUNTER_SIZE_8BIT: while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT8.COUNT.reg = config->counter_8_bit.value; while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT8.PER.reg = config->counter_8_bit.period; while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT8.CC[0].reg = config->counter_8_bit.compare_capture_channel[0]; while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT8.CC[1].reg = config->counter_8_bit.compare_capture_channel[1]; return STATUS_OK; case TC_COUNTER_SIZE_16BIT: while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT16.COUNT.reg = config->counter_16_bit.value; while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT16.CC[0].reg = config->counter_16_bit.compare_capture_channel[0]; while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT16.CC[1].reg = config->counter_16_bit.compare_capture_channel[1]; return STATUS_OK; case TC_COUNTER_SIZE_32BIT: while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT32.COUNT.reg = config->counter_32_bit.value; while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT32.CC[0].reg = config->counter_32_bit.compare_capture_channel[0]; while (tc_is_syncing(module_inst)) { /* Wait for sync */ } hw->COUNT32.CC[1].reg = config->counter_32_bit.compare_capture_channel[1]; return STATUS_OK; } Assert(false); return STATUS_ERR_INVALID_ARG; }