bool mgos_uart_hal_init(struct mgos_uart_state *us) {
/* Start with ints disabled. */
WRITE_PERI_REG(UART_INT_ENA(us->uart_no), 0);
#ifdef RTOS_SDK
_xt_isr_mask(1 << ETS_UART_INUM);
_xt_isr_attach(ETS_UART_INUM, (void *) esp_uart_isr, NULL);
#else
ETS_INTR_DISABLE(ETS_UART_INUM);
ETS_UART_INTR_ATTACH(esp_uart_isr, NULL);
#endif
return true;
}
IRAM void uart0_rx_handler(void)
{
// TODO: Handle UART1, see reg 0x3ff20020, bit2, bit0 represents uart1 and uart0 respectively
if (!UART(UART0).INT_STATUS & UART_INT_STATUS_RXFIFO_FULL) {
return;
}
// printf(" [%08x (%d)]\n", READ_PERI_REG(UART_INT_ST(UART0)), READ_PERI_REG(UART_STATUS(UART0)) & (UART_RXFIFO_CNT << UART_RXFIFO_CNT_S));
if (UART(UART0).INT_STATUS & UART_INT_STATUS_RXFIFO_FULL) {
UART(UART0).INT_CLEAR = UART_INT_CLEAR_RXFIFO_FULL;
if (UART(UART0).STATUS & (UART_STATUS_RXFIFO_COUNT_M << UART_STATUS_RXFIFO_COUNT_S)) {
long int xHigherPriorityTaskWoken;
_xt_isr_mask(1 << INUM_UART);
_xt_clear_ints(1<<INUM_UART);
xSemaphoreGiveFromISR(uart0_sem, &xHigherPriorityTaskWoken);
if(xHigherPriorityTaskWoken) {
portYIELD();
}
}
} else {
printf("Error: unexpected uart irq, INT_STATUS 0x%02x\n", UART(UART0).INT_STATUS);
}
}
bool mgos_uart_hal_configure(struct mgos_uart_state *us,
const struct mgos_uart_config *cfg) {
if (!esp_uart_validate_config(cfg)) return false;
#ifdef RTOS_SDK
_xt_isr_mask(1 << ETS_UART_INUM);
#else
ETS_INTR_DISABLE(ETS_UART_INUM);
#endif
uart_div_modify(us->uart_no, UART_CLK_FREQ / cfg->baud_rate);
if (us->uart_no == 0) {
if (cfg->dev.swap_rxcts_txrts) {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_MTCK_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 4 /* FUNC_U0CTS */);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
SET_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART0_PIN_SWAP);
} else {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_U0TXD_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_U0TXD);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0RXD_U, 0 /* FUNC_U0RXD */);
CLEAR_PERI_REG_MASK(PERIPHS_DPORT_BASEADDR + HOST_INF_SEL,
PERI_IO_UART0_PIN_SWAP);
}
} else {
if (cfg->dev.swap_rxcts_txrts) {
/* Swapping pins of UART1 is not supported, they all conflict with SPI
* flash anyway. */
return false;
} else {
PIN_PULLUP_DIS(PERIPHS_IO_MUX_GPIO2_U);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_U1TXD_BK);
}
}
unsigned int conf0 = 0;
switch (cfg->num_data_bits) {
case 5:
break;
case 6:
conf0 |= 1 << UART_BIT_NUM_S;
break;
case 7:
conf0 |= 2 << UART_BIT_NUM_S;
break;
case 8:
conf0 |= 3 << UART_BIT_NUM_S;
break;
default:
return false;
}
switch (cfg->parity) {
case MGOS_UART_PARITY_NONE:
break;
case MGOS_UART_PARITY_EVEN:
conf0 |= UART_PARITY_EN;
break;
case MGOS_UART_PARITY_ODD:
conf0 |= (UART_PARITY_EN | UART_PARITY_ODD);
break;
}
switch (cfg->stop_bits) {
case MGOS_UART_STOP_BITS_1:
conf0 |= 1 << UART_STOP_BIT_NUM_S;
break;
case MGOS_UART_STOP_BITS_1_5:
conf0 |= 2 << UART_STOP_BIT_NUM_S;
break;
case MGOS_UART_STOP_BITS_2:
conf0 |= 3 << UART_STOP_BIT_NUM_S;
break;
}
if (cfg->tx_fc_type == MGOS_UART_FC_HW) {
conf0 |= UART_TX_FLOW_EN;
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, FUNC_U0CTS);
}
WRITE_PERI_REG(UART_CONF0(us->uart_no), conf0);
unsigned int conf1 = cfg->dev.rx_fifo_full_thresh;
conf1 |= (cfg->dev.tx_fifo_empty_thresh << 8);
if (cfg->dev.rx_fifo_alarm >= 0) {
conf1 |= UART_RX_TOUT_EN | ((cfg->dev.rx_fifo_alarm & 0x7f) << 24);
}
if (cfg->rx_fc_type == MGOS_UART_FC_HW && cfg->dev.rx_fifo_fc_thresh > 0) {
/* UART_RX_FLOW_EN will be set in uart_start. */
conf1 |= ((cfg->dev.rx_fifo_fc_thresh & 0x7f) << 16);
PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_U0RTS);
}
WRITE_PERI_REG(UART_CONF1(us->uart_no), conf1);
#ifdef RTOS_SDK
_xt_isr_unmask(1 << ETS_UART_INUM);
#else
ETS_INTR_ENABLE(ETS_UART_INUM);
#endif
return true;
}
