void post_cache_as_ram(void)
{
void *resume_backup_memory = NULL;
uint32_t family = amd_fam1x_cpu_family();
/* Verify that the BSP didn't overrun the lower stack
* boundary during romstage execution
*/
volatile uint32_t *lower_stack_boundary;
lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_DCACHE_BSP_STACK_SIZE);
if ((*lower_stack_boundary) != 0xdeadbeef)
printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n");
struct romstage_handoff *handoff;
handoff = romstage_handoff_find_or_add();
if (handoff != NULL)
handoff->s3_resume = acpi_is_wakeup_s3();
else
printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");
int s3resume = acpi_is_wakeup_s3();
if (s3resume) {
cbmem_recovery(s3resume);
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
}
prepare_romstage_ramstack(resume_backup_memory);
/* from here don't store more data in CAR */
if (family >= 0x1f && family <= 0x3f) {
/* Family 10h and 12h, 11h until shown otherwise */
vErrata343();
}
size_t car_size = car_data_size();
void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);
print_car_debug("Copying data from cache to RAM...");
memcpy_(migrated_car, _car_relocatable_data_start, car_size);
print_car_debug(" Done\n");
print_car_debug("Verifying data integrity in RAM...");
if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0)
print_car_debug(" Done\n");
else
print_car_debug(" FAILED\n");
/* New stack grows right below migrated_car. */
print_car_debug("Switching to use RAM as stack...");
cache_as_ram_switch_stack(migrated_car);
/* We do not come back. */
}
static void mainboard_enable(device_t dev)
{
u16 pmbase;
dev->ops->init = mainboard_init;
dev->ops->acpi_fill_ssdt_generator = fill_ssdt;
pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
PMBASE) & 0xff80;
printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
outl(0, pmbase + SMI_EN);
enable_lapic();
pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE,
DEFAULT_GPIOBASE | 1);
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL,
0x10);
/* If we're resuming from suspend, blink suspend LED */
if (acpi_is_wakeup_s3())
ec_write(0x0c, 0xc7);
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2);
}
/**********************************************
* enable the dedicated function in mainboard.
**********************************************/
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
}
void mainboard_ec_init(void)
{
printk(BIOS_DEBUG, "mainboard: EC init\n");
if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */
google_chromeec_set_smi_mask(0);
/* Clear pending events */
while (google_chromeec_get_event() != 0)
;
/* Restore SCI event mask */
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
}
/* Clear wake event mask */
google_chromeec_set_wake_mask(0);
}
static void wilco_ec_init(struct device *dev)
{
if (!dev->enabled)
return;
/* Disable S0ix support in EC RAM with ACPI EC interface */
if (!acpi_is_wakeup_s3()) {
ec_set_ports(CONFIG_EC_BASE_ACPI_COMMAND,
CONFIG_EC_BASE_ACPI_DATA);
ec_write(EC_RAM_S0IX_SUPPORT, 0);
}
/* Print EC firmware information */
wilco_ec_print_all_info();
/* Initialize keyboard, ignore emulated PS/2 mouse */
pc_keyboard_init(NO_AUX_DEVICE);
/* Direct power button to the host for processing */
wilco_ec_send(KB_POWER_BUTTON_TO_HOST, 1);
/* Unmute speakers */
wilco_ec_send(KB_HW_MUTE_CONTROL, AUDIO_UNMUTE_125MS);
/* Enable WiFi radio */
wilco_ec_radio_control(RADIO_WIFI, 1);
/* Turn on camera power */
wilco_ec_send(KB_CAMERA, CAMERA_ON);
}
/* Prepare ports to be routed to EHCI or XHCI */
static void xhci_route_all(device_t dev)
{
static const struct reg_script xhci_route_all_script[] = {
/* USB3 SuperSpeed Enable */
REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP),
/* USB2 Port Route to XHCI */
REG_PCI_WRITE32(XHCI_USB2PR, BYTM_USB2_PORT_MAP),
REG_SCRIPT_END
};
u32 port_disabled;
int port;
printk(BIOS_INFO, "USB: Route ports to XHCI controller\n");
/* Route ports to XHCI controller */
reg_script_run_on_dev(dev, xhci_route_all_script);
if (acpi_is_wakeup_s3())
return;
/* Reset enabled USB3 ports */
port_disabled = pci_read_config32(dev, XHCI_USB3PDO);
for (port = 0; port < BYTM_USB3_PORT_COUNT; port++) {
if (port_disabled & (1 << port))
continue;
xhci_reset_port_usb3(dev, port);
}
}
void *backup_default_smm_area(void)
{
void *save_area;
const void *default_smm = (void *)SMM_DEFAULT_BASE;
if (!IS_ENABLED(CONFIG_HAVE_ACPI_RESUME))
return NULL;
/*
* The buffer needs to be preallocated regardless. In the non-resume
* path it will be allocated for handling resume. Note that cbmem_add()
* does a find before the addition.
*/
save_area = cbmem_add(CBMEM_ID_SMM_SAVE_SPACE, SMM_DEFAULT_SIZE);
if (save_area == NULL) {
printk(BIOS_DEBUG, "SMM save area not added.\n");
return NULL;
}
/* Only back up the area on S3 resume. */
if (acpi_is_wakeup_s3()) {
memcpy(save_area, default_smm, SMM_DEFAULT_SIZE);
return save_area;
}
/*
* Not the S3 resume path. No need to restore memory contents after
* SMM relocation.
*/
return NULL;
}
static void usb_xhci_init(struct device *dev)
{
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
u32 reg32;
u16 reg16;
config_t *config = dev->chip_info;
/* D20:F0:74h[1:0] = 00b (set D0 state) */
reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS);
reg16 &= ~PWR_CTL_SET_MASK;
reg16 |= PWR_CTL_SET_D0;
pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16);
/* Disable Compliance Mode Entry */
reg32 = read32(res2mmio(res, 0x80ec, 0));
reg32 |= (1 << 0);
write32(res2mmio(res, 0x80ec, 0), reg32);
/* Enable clock gating first */
usb_xhci_clock_gating(dev);
if (acpi_is_wakeup_s3()) {
/* Reset ports that are disabled or
* polling before returning to the OS. */
usb_xhci_reset_usb3(dev, 0);
} else if (config->xhci_default) {
/* Route all ports to XHCI */
outb(0xca, 0xb2);
}
}
void broadwell_run_reference_code(void)
{
int ret, dummy;
struct pei_data pei_data;
pei_wrapper_entry_t entry;
memset(&pei_data, 0, sizeof(pei_data));
mainboard_fill_pei_data(&pei_data);
broadwell_fill_pei_data(&pei_data);
pei_data.boot_mode = acpi_is_wakeup_s3() ? SLEEP_STATE_S3 : 0;
pei_data.saved_data = (void *) &dummy;
entry = load_reference_code();
if (entry == NULL) {
printk(BIOS_ERR, "Reference code not found\n");
return;
}
/* Call into reference code. */
ret = entry(&pei_data);
if (ret != 0) {
printk(BIOS_ERR, "Reference code returned %d\n", ret);
return;
}
}
static void mainboard_init(struct device *dev)
{
struct southbridge_intel_i82801gx_config *config;
struct device *idedev;
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
GMA_INT15_PANEL_FIT_DEFAULT,
PANEL, 3);
/* If we're resuming from suspend, blink suspend LED */
if (acpi_is_wakeup_s3())
ec_write(0x0c, 0xc7);
idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1));
if (!(inb(DEFAULT_GPIOBASE + 0x0c) & 0x40)) {
/* legacy I/O connected */
pmh7_ultrabay_power_enable(1);
ec_write(0x0c, 0x84);
} else if (idedev && idedev->chip_info &&
h8_ultrabay_device_present()) {
config = idedev->chip_info;
config->ide_enable_primary = 1;
pmh7_ultrabay_power_enable(1);
ec_write(0x0c, 0x84);
} else {
pmh7_ultrabay_power_enable(0);
ec_write(0x0c, 0x04);
}
/* set dock status led */
ec_write(0x0c, 0x08);
ec_write(0x0c, inb(0x164c) & 8 ? 0x89 : 0x09);
}
static pei_wrapper_entry_t load_reference_code(void)
{
struct prog prog =
PROG_INIT(ASSET_REFCODE, CONFIG_CBFS_PREFIX "/refcode");
struct rmod_stage_load refcode = {
.cbmem_id = CBMEM_ID_REFCODE,
.prog = &prog,
};
if (acpi_is_wakeup_s3()) {
return load_refcode_from_cache();
}
if (prog_locate(&prog)) {
printk(BIOS_DEBUG, "Couldn't locate reference code.\n");
return NULL;
}
if (rmodule_stage_load(&refcode)) {
printk(BIOS_DEBUG, "Error loading reference code.\n");
return NULL;
}
/* Cache loaded reference code. */
stage_cache_add(STAGE_REFCODE, &prog);
return (pei_wrapper_entry_t)prog_entry(&prog);
}
static void copy_secondary_start_to_lowest_1M(void)
{
unsigned long code_size;
/* Fill in secondary_start's local gdt. */
setup_secondary_gdt();
code_size = (unsigned long)_secondary_start_end
- (unsigned long)_secondary_start;
if (acpi_is_wakeup_s3()) {
/* need to save it for RAM resume */
lowmem_backup_size = code_size;
lowmem_backup = malloc(code_size);
lowmem_backup_ptr = (char *)AP_SIPI_VECTOR;
if (lowmem_backup == NULL)
die("Out of backup memory\n");
memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
}
/* copy the _secondary_start to the RAM below 1M*/
memcpy((unsigned char *)AP_SIPI_VECTOR,
(unsigned char *)_secondary_start, code_size);
printk(BIOS_DEBUG, "start_eip=0x%08lx, code_size=0x%08lx\n",
(unsigned long int)AP_SIPI_VECTOR, code_size);
}
void mainboard_ec_init(void)
{
printk(BIOS_DEBUG, "mainboard_ec_init\n");
post_code(0xf0);
/* Restore SCI event mask on resume. */
if (acpi_is_wakeup_s3()) {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S3_WAKE_EVENTS);
/* Disable SMI and wake events */
google_chromeec_set_smi_mask(0);
/* Clear pending events */
while (google_chromeec_get_event() != 0)
;
google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
}
/* Clear wake events, these are enabled on entry to sleep */
google_chromeec_set_wake_mask(0);
post_code(0xf1);
}
void cache_as_ram_new_stack (void)
{
void *resume_backup_memory = NULL;
print_car_debug("Top about %08x ... Done\n", (uint32_t) &resume_backup_memory);
print_car_debug("Disabling cache as ram now\n");
disable_cache_as_ram_bsp();
disable_cache();
/* Enable cached access to RAM in the range 1M to CONFIG_RAMTOP */
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
if (acpi_is_wakeup_s3()) {
resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
print_car_debug("Resume backup memory location: %p\n", resume_backup_memory);
}
prepare_ramstage_region(resume_backup_memory);
set_sysinfo_in_ram(1); // So other core0 could start to train mem
/*copy and execute ramstage */
copy_and_run();
/* We will not return */
print_car_debug("should not be here -\n");
}
static void smm_install(void)
{
/* The first CPU running this gets to copy the SMM handler. But not all
* of them.
*/
if (smm_handler_copied)
return;
smm_handler_copied = 1;
/* if we're resuming from S3, the SMM code is already in place,
* so don't copy it again to keep the current SMM state */
if (!acpi_is_wakeup_s3()) {
/* enable the SMM memory window */
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
D_OPEN | G_SMRAME | C_BASE_SEG);
/* copy the real SMM handler */
memcpy((void *)0xa0000, _binary_smm_start,
_binary_smm_end - _binary_smm_start);
wbinvd();
}
/* close the SMM memory window and enable normal SMM */
pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
G_SMRAME | C_BASE_SEG);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
amd_initmmio();
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
post_code(0x31);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x38);
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
post_code(0x39);
AGESAWRAPPER(amdinitearly);
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
AGESAWRAPPER(amdinitpost);
post_code(0x41);
AGESAWRAPPER(amdinitenv);
/* TODO: Disable cache is not ok. */
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
AGESAWRAPPER(amdinitresume);
AGESAWRAPPER(amds3laterestore);
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
}
static void pch_set_acpi_mode(void)
{
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) {
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT);
printk(BIOS_DEBUG, "done.\n");
}
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
post_code(0x31);
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x42);
agesawrapper_amdinitenv();
amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
agesawrapper_amdinitresume();
agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */
}
void *GetHeapBase(void)
{
void *heap = (void *)BIOS_HEAP_START_ADDRESS;
if (acpi_is_wakeup_s3())
heap = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
return heap;
}
/**********************************************
* Enable the dedicated functions of the board.
**********************************************/
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
/* Initialize the PIRQ data structures for consumption */
pirq_setup();
}
static void igd_init(struct device *dev)
{
if (IS_ENABLED(CONFIG_GOP_SUPPORT))
return;
/* IGD needs to be Bus Master */
u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
pci_write_config32(dev, PCI_COMMAND, reg32);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!gtt_res || !gtt_res->base)
return;
/* Wait for any configured pre-graphics delay */
if (!acpi_is_wakeup_s3()) {
#if IS_ENABLED(CONFIG_CHROMEOS)
if (developer_mode_enabled() || recovery_mode_enabled() ||
vboot_wants_oprom())
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
#else
mdelay(CONFIG_PRE_GRAPHICS_DELAY);
#endif
}
/* Initialize PCI device, load/execute BIOS Option ROM */
pci_dev_init(dev);
#if IS_ENABLED(CONFIG_CHROMEOS)
if (!gfx_get_init_done() && !acpi_is_wakeup_s3()) {
/*
* Enable DDI-A if the Option ROM did not execute:
*
* bit 0: Display detected (RO)
* bit 4: DDI A supports 4 lanes and DDI E is not used
* bit 7: DDI buffer is idle
*/
gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES |
DDI_INIT_DISPLAY_DETECTED);
}
#endif
}
static void init_tpm_dev(void *unused)
{
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
int s3resume = acpi_is_wakeup_s3();
tpm_setup(s3resume);
#else
/* This can lead to PCR reset attacks but currently there
is no generic way to detect resume on other platforms. */
tpm_setup(false);
#endif
}
UINT32 GetHeapBase(AMD_CONFIG_PARAMS *StdHeader)
{
UINT32 heap = BIOS_HEAP_START_ADDRESS;
if (acpi_is_wakeup_s3())
heap = (UINT32) cbmem_find(CBMEM_ID_RESUME_SCRATCH) +
(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE);
/* himem_heap_base + high_stack_size */
return heap;
}
static void s3_resume_prepare(void)
{
global_nvs_t *gnvs;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
if (gnvs == NULL)
return;
if (!acpi_is_wakeup_s3())
memset(gnvs, 0, sizeof(global_nvs_t));
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
amd_initmmio();
hudson_lpc_port80();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
post_code(0x31);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
agesawrapper_amdinitpost();
post_code(0x41);
agesawrapper_amdinitenv();
disable_cache_as_ram();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
agesawrapper_amdinitresume();
amd_initcpuio();
agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
post_code(0x54); /* Should never see this post code. */
}
static void i82801ix_lock_smm(struct device *dev)
{
#if TEST_SMM_FLASH_LOCKDOWN
u8 reg8;
#endif
if (!acpi_is_wakeup_s3()) {
#if ENABLE_ACPI_MODE_IN_COREBOOT
printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT); // Enable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#else
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode
printk(BIOS_DEBUG, "done.\n");
#endif
} else {
printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n");
outb(APM_CNT_ACPI_ENABLE, APM_CNT);
}
/* Don't allow evil boot loaders, kernels, or
* userspace applications to deceive us:
*/
smm_lock();
#if TEST_SMM_FLASH_LOCKDOWN
/* Now try this: */
printk(BIOS_DEBUG, "Locking BIOS to RO... ");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
reg8 &= ~(1 << 0); /* clear BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 |= (1 << 1); /* set BLE */
pci_write_config8(dev, 0xdc, reg8);
printk(BIOS_DEBUG, "ok.\n");
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Writing:\n");
*(volatile u8 *)0xfff00000 = 0x00;
printk(BIOS_DEBUG, "Testing:\n");
reg8 |= (1 << 0); /* set BIOSWE */
pci_write_config8(dev, 0xdc, reg8);
reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
(reg8&1)?"rw":"ro");
printk(BIOS_DEBUG, "Done.\n");
#endif
}
void *vbt_get(void)
{
if (!IS_ENABLED(CONFIG_RUN_FSP_GOP))
return NULL;
/* Normal mode and S3 resume path PEIM GFX init is not needed.
* Passing NULL as VBT will not make PEIM GFX to execute. */
if (acpi_is_wakeup_s3())
return NULL;
if (!display_init_required())
return NULL;
return locate_vbt(NULL);
}
static void mainboard_enable(device_t dev)
{
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
hudson_enable_smi_generation();
if (acpi_is_wakeup_s3())
agesawrapper_fchs3earlyrestore();
else
pavilion_cold_boot_init();
}
void *GetHeapBase(void)
{
void *heap = (void *)BIOS_HEAP_START_ADDRESS;
if (acpi_is_wakeup_s3()) {
/* FIXME: For S3 resume path, buffer is in CBMEM
* with some arbitrary header. */
heap = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
heap += 0x10;
}
return heap;
}
static void mainboard_enable(struct device *dev)
{
dev->ops->get_smbios_strings = mainboard_smbios_strings,
install_intel_vga_int15_handler(
GMA_INT15_ACTIVE_LFP_INT_LVDS,
GMA_INT15_PANEL_FIT_DEFAULT,
GMA_INT15_BOOT_DISPLAY_DEFAULT,
0);
if (!acpi_is_wakeup_s3())
lenovo_s230u_ec_init();
}
