/**
* Set the RX and TX path rates.
* @param phy The AD9361 state structure.
* @param rx_path_clks RX path rates buffer.
* @param tx_path_clks TX path rates buffer.
* @return 0 in case of success, negative error code otherwise.
*/
int32_t ad9361_set_trx_path_clks(struct ad9361_rf_phy *phy,
uint32_t *rx_path_clks,
uint32_t *tx_path_clks)
{
int32_t ret;
ret = ad9361_set_trx_clock_chain(phy, rx_path_clks, tx_path_clks);
if (ret < 0)
return ret;
ret = ad9361_update_rf_bandwidth(phy, phy->current_rx_bw_Hz,
phy->current_tx_bw_Hz);
return ret;
}
/**
* Set the TX sampling frequency.
* @param phy The AD9361 current state structure.
* @param sampling_freq_hz The desired frequency (Hz).
* @return 0 in case of success, negative error code otherwise.
*/
int32_t ad9361_set_tx_sampling_freq (struct ad9361_rf_phy *phy,
uint32_t sampling_freq_hz)
{
int32_t ret;
uint32_t rx[6], tx[6];
ret = ad9361_calculate_rf_clock_chain(phy, sampling_freq_hz,
phy->rate_governor, rx, tx);
if (ret < 0)
return ret;
ad9361_set_trx_clock_chain(phy, rx, tx);
ret = ad9361_update_rf_bandwidth(phy, phy->current_rx_bw_Hz,
phy->current_tx_bw_Hz);
return ret;
}
/**
* Setup the AD9361 device.
* @param phy The AD9361 state structure.
* @return 0 in case of success, negative error code otherwise.
*/
int32_t ad9361_post_setup(struct ad9361_rf_phy *phy)
{
struct axiadc_converter *conv = phy->adc_conv;
struct axiadc_state *st = phy->adc_state;
int32_t rx2tx2 = phy->pdata->rx2tx2;
int32_t tmp, num_chan, flags;
int32_t i, ret;
num_chan = (conv->chip_info->num_channels > 4) ? 4 : conv->chip_info->num_channels;
axiadc_write(st, ADI_REG_CNTRL, rx2tx2 ? 0 : ADI_R1_MODE);
tmp = axiadc_read(st, 0x4048);
if (!rx2tx2) {
axiadc_write(st, 0x4048, tmp | BIT(5)); /* R1_MODE */
axiadc_write(st, 0x404c,
(phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) ? 1 : 0); /* RATE */
}
else {
tmp &= ~BIT(5);
axiadc_write(st, 0x4048, tmp);
axiadc_write(st, 0x404c,
(phy->pdata->port_ctrl.pp_conf[2] & LVDS_MODE) ? 3 : 1); /* RATE */
}
#ifdef ALTERA_PLATFORM
axiadc_write(st, 0x404c, 1);
#endif
for (i = 0; i < num_chan; i++) {
axiadc_write(st, ADI_REG_CHAN_CNTRL_1(i),
ADI_DCFILT_OFFSET(0));
axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i),
(i & 1) ? 0x00004000 : 0x40000000);
axiadc_write(st, ADI_REG_CHAN_CNTRL(i),
ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE |
ADI_ENABLE | ADI_IQCOR_ENB);
}
flags = 0x0;
ret = ad9361_dig_tune(phy, ((conv->chip_info->num_channels > 4) ||
axiadc_read(st, 0x0004)) ? 0 : 61440000, flags);
if (ret < 0)
return ret;
if (flags & (DO_IDELAY | DO_ODELAY)) {
ret = ad9361_dig_tune(phy, (axiadc_read(st, ADI_REG_ID)) ?
0 : 61440000, flags & BE_VERBOSE);
if (ret < 0)
return ret;
}
ret = ad9361_set_trx_clock_chain(phy,
phy->pdata->rx_path_clks,
phy->pdata->tx_path_clks);
ad9361_ensm_force_state(phy, ENSM_STATE_ALERT);
ad9361_ensm_restore_prev_state(phy);
return ret;
}