コード例 #1
0
ファイル: xcomm.c プロジェクト: TheBigCheese/no-OS
/**************************************************************************//**
* @brief Calibrates the ADC DCO clock delay 
* 
* @return If success, returns DCO clock delay code. If the DCO clock is
* 		  inverted 0x100 is added to the returned DCO value
*		  if error,return -1
******************************************************************************/
int32_t XCOMM_CalibrateAdcDco(void)
{
	int32_t ret;

	ADC_Core_Write(ADC_CORE_DMA_CHAN_SEL,0x00);

	ad9643_dco_clock_invert(0);
	ret = ad9643_dco_calibrate_2c();

	ADC_Core_Write(ADC_CORE_DMA_CHAN_SEL,0x02);

	return ret;
}
コード例 #2
0
ファイル: xcomm.c プロジェクト: DrSutherland/no-OS
/**************************************************************************//**
* @brief Calibrates the ADC DCO clock delay 
* 
* @return If success, returns DCO clock delay code
*		  if error,return -1
******************************************************************************/
int32_t XCOMM_CalibrateAdcDco(void)
{
	int32_t ret;

	ADC_Core_Write(ADC_CORE_DMA_CHAN_SEL,0x00);

	ad9643_dco_clock_invert(0);
	ret = ad9643_dco_calibrate_2c();

	if(ret<0)
	{
		ad9643_dco_clock_invert(1);
		ret = ad9643_dco_calibrate_2c();
                if (!(ret<0))
                {
                    ret |= 0x0100;
                }

	}

	ADC_Core_Write(ADC_CORE_DMA_CHAN_SEL,0x02);

	return ret;
}
コード例 #3
0
ファイル: AD9643.c プロジェクト: DrSutherland/no-OS
/***************************************************************************//**
 * @brief Initializes the AD9643. 
 *
 * @return Negative error code or 0 in case of success.
*******************************************************************************/
int32_t ad9643_setup()
{
    int32_t ret = 0;
	
	ad9643_reset();
	ad9643_write(AD9643_REG_CLK_PHASE_CTRL, AD9643_CLK_PHASE_CTRL_EVEN_ODD_MODE_EN);
    ADC_Core_Write(ADC_CORE_ADC_CTRL,ADC_CORE_SIGNEXTEND | ADC_CORE_SCALE_OFFSET_EN);
    ADC_Core_Write(ADC_CORE_CA_OFFS_SCALE,ADC_CORE_OFFSET(0) | ADC_CORE_SCALE(0x8000));
    ADC_Core_Write(ADC_CORE_CB_OFFS_SCALE,ADC_CORE_OFFSET(0) | ADC_CORE_SCALE(0x8000));
	ad9643_write(AD9643_REG_OUTPUT_MODE, AD9643_OUTPUT_MODE_DEF | AD9643_OUTPUT_MODE_TWOS_COMPLEMENT);
	ad9643_write(AD9643_REG_TEST_MODE, AD9643_TEST_MODE_OFF);
	ad9643_write(AD9643_REG_TRANSFER, AD9643_TRANSFER_EN);

	ret = ad9643_dco_calibrate_2c();
	if(ret < 0)
	{
		ad9643_dco_clock_invert(1);
		ret = ad9643_dco_calibrate_2c();
	}

    ADC_Core_Write(ADC_CORE_DMA_CHAN_SEL,0x02);

	return ret < 0 ? -1 : 0;
}