static void
add_regs_scalar_1(struct fd2_compile_context *ctx,
struct tgsi_full_instruction *inst, struct ir2_instruction *alu)
{
assert(inst->Instruction.NumSrcRegs == 1);
assert(inst->Instruction.NumDstRegs == 1);
add_dst_reg(ctx, alu, &inst->Dst[0].Register);
add_src_reg(ctx, alu, &inst->Src[0].Register);
add_scalar_clamp(inst, alu);
}
/* POW(a,b) = EXP2(b * LOG2(a)) */
static void
translate_pow(struct fd2_compile_context *ctx,
struct tgsi_full_instruction *inst)
{
struct tgsi_dst_register tmp_dst;
struct tgsi_src_register tmp_src;
struct ir2_instruction *alu;
get_internal_temp(ctx, &tmp_dst, &tmp_src);
alu = ir2_instr_create_alu(next_exec_cf(ctx), ~0, LOG_CLAMP);
add_regs_dummy_vector(alu);
add_dst_reg(ctx, alu, &tmp_dst);
add_src_reg(ctx, alu, &inst->Src[0].Register);
alu = ir2_instr_create_alu(next_exec_cf(ctx), MULv, ~0);
add_dst_reg(ctx, alu, &tmp_dst);
add_src_reg(ctx, alu, &tmp_src);
add_src_reg(ctx, alu, &inst->Src[1].Register);
/* NOTE: some of the instructions, like EXP_IEEE, seem hard-
* coded to take their input from the w component.
*/
switch(inst->Dst[0].Register.WriteMask) {
case TGSI_WRITEMASK_X:
tmp_src.SwizzleW = TGSI_SWIZZLE_X;
break;
case TGSI_WRITEMASK_Y:
tmp_src.SwizzleW = TGSI_SWIZZLE_Y;
break;
case TGSI_WRITEMASK_Z:
tmp_src.SwizzleW = TGSI_SWIZZLE_Z;
break;
case TGSI_WRITEMASK_W:
tmp_src.SwizzleW = TGSI_SWIZZLE_W;
break;
default:
DBG("invalid writemask!");
assert(0);
break;
}
alu = ir2_instr_create_alu(next_exec_cf(ctx), ~0, EXP_IEEE);
add_regs_dummy_vector(alu);
add_dst_reg(ctx, alu, &inst->Dst[0].Register);
add_src_reg(ctx, alu, &tmp_src);
add_scalar_clamp(inst, alu);
}
