void maca_isr(void) {
// print_packets("maca_isr");
maca_entry++;
if (bit_is_set(*MACA_STATUS, maca_status_ovr))
{ PRINTF("maca overrun\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_busy))
{ PRINTF("maca busy\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_crc))
{ PRINTF("maca crc error\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_to))
{ PRINTF("maca timeout\n\r"); }
if (data_indication_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_di);
dma_rx->length = *MACA_GETRXLVL - 2; /* packet length does not include FCS */
// PRINTF("maca data ind %x %d\n\r", dma_rx, dma_rx->length);
if(maca_rx_callback != 0) { maca_rx_callback(dma_rx); }
add_to_rx(dma_rx);
dma_rx = 0;
}
if (filter_failed_irq()) {
PRINTF("maca filter failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_flt);
}
if (checksum_failed_irq()) {
PRINTF("maca checksum failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_crc);
}
if (softclock_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_sftclk);
}
if (poll_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_poll);
}
if(action_complete_irq()) {
/* PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE)); */
if(last_post == TX_POST) {
if(maca_tx_callback != 0) { maca_tx_callback(tx_head); }
dma_tx = 0;
free_tx_head();
last_post = NO_POST;
}
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_acpl);
}
decode_status();
if (*MACA_IRQ != 0)
{ PRINTF("*MACA_IRQ %x\n\r", *MACA_IRQ); }
if(tx_head != 0) {
post_tx();
} else {
post_receive();
}
}
void maca_isr(void) {
// print_packets("maca_isr");
maca_entry++;
if (bit_is_set(*MACA_STATUS, maca_status_ovr))
{ PRINTF("maca overrun\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_busy))
{ PRINTF("maca busy\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_crc))
{ PRINTF("maca crc error\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_to))
{ PRINTF("maca timeout\n\r"); }
if (data_indication_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_di);
if (dma_rx != &dummy_ack && dma_rx != &dummy_rx)
{
dma_rx->length = *MACA_GETRXLVL - 2; /* packet length does not include FCS */
dma_rx->lqi = get_lqi();
dma_rx->rx_time = *MACA_TIMESTAMP;
/* check if received packet needs an ack */
if(prm_mode == AUTOACK && (dma_rx->data[1] & 0x20)) {
/* this wait is necessary to auto-ack */
volatile uint32_t wait_clk;
wait_clk = *MACA_CLK + 200;
while(*MACA_CLK < wait_clk) { continue; }
}
if(maca_rx_callback != 0) { maca_rx_callback(dma_rx); }
add_to_rx(dma_rx);
}
dma_rx = 0;
}
if (filter_failed_irq()) {
PRINTF("maca filter failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_flt);
}
if (checksum_failed_irq()) {
PRINTF("maca checksum failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_crc);
}
if (softclock_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_sftclk);
}
if (poll_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_poll);
}
if(action_complete_irq()) {
/* PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE)); */
if(last_post == TX_POST) {
tx_head->status = get_field(*MACA_STATUS,CODE);
#if MACA_INSERT_ACK
/* Having sent a message with the acknowledge request flag set the
* MACA hardware will only give a tx success indication if the message
* was acknowledged by the remote node. We need to detect this
* condition and inject an ACK packet into the internal receive stream
* as the higher layers are expecting to see an ACK packet.*/
if(tx_head->status == SUCCESS && (tx_head->data[0] & MAC_ACK_REQUEST_FLAG)) {
/* Create the dummy ack packet */
static volatile packet_t *ack_p;
if(ack_p = get_free_packet()) {
ack_p->length = 3;
ack_p->offset = 1;
ack_p->data[0] = 3;
ack_p->data[1] = 0x02;
ack_p->data[2] = 0;
ack_p->data[3] = *MACA_TXSEQNR;
insert_at_rx_head(ack_p);
}
}
#endif
if(maca_tx_callback != 0) { maca_tx_callback(tx_head); }
dma_tx = 0;
free_tx_head();
last_post = NO_POST;
}
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_acpl);
}
decode_status();
if (*MACA_IRQ != 0)
{ PRINTF("*MACA_IRQ %x\n\r", (unsigned int)*MACA_IRQ); }
if(tx_head != 0) {
post_tx();
} else {
post_receive();
}
}
void maca_isr(void) {
// print_packets("maca_isr");
maca_entry++;
if (bit_is_set(*MACA_STATUS, maca_status_ovr))
{ PRINTF("maca overrun\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_busy))
{ PRINTF("maca busy\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_crc))
{ PRINTF("maca crc error\n\r"); }
if (bit_is_set(*MACA_STATUS, maca_status_to))
{ PRINTF("maca timeout\n\r"); }
if (data_indication_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_di);
dma_rx->length = *MACA_GETRXLVL - 2; /* packet length does not include FCS */
dma_rx->lqi = get_lqi();
dma_rx->rx_time = *MACA_TIMESTAMP;
/* check if received packet needs an ack */
if(dma_rx->data[1] & 0x20) {
/* this wait is necessary to auto-ack */
volatile uint32_t wait_clk;
wait_clk = *MACA_CLK + 200;
while(*MACA_CLK < wait_clk) { continue; }
}
if(maca_rx_callback != 0) { maca_rx_callback(dma_rx); }
add_to_rx(dma_rx);
dma_rx = 0;
}
if (filter_failed_irq()) {
PRINTF("maca filter failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_flt);
}
if (checksum_failed_irq()) {
PRINTF("maca checksum failed\n\r");
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_crc);
}
if (softclock_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_sftclk);
}
if (poll_irq()) {
*MACA_CLRIRQ = (1 << maca_irq_poll);
}
if(action_complete_irq()) {
/* PRINTF("maca action complete %d\n\r", get_field(*MACA_CONTROL,SEQUENCE)); */
if(last_post == TX_POST) {
tx_head->status = get_field(*MACA_STATUS,CODE);
if(maca_tx_callback != 0) { maca_tx_callback(tx_head); }
dma_tx = 0;
free_tx_head();
last_post = NO_POST;
}
ResumeMACASync();
*MACA_CLRIRQ = (1 << maca_irq_acpl);
}
decode_status();
if (*MACA_IRQ != 0)
{ PRINTF("*MACA_IRQ %x\n\r", (unsigned int)*MACA_IRQ); }
if(tx_head != 0) {
post_tx();
} else {
post_receive();
}
}