static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
/*
* QE12 is muxed with LBCTL, it needs to be released for enabling
* LBCTL signal for LBC usage.
*/
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
/* Adjust the interface according to speed */
adjust_link(dev);
}
static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
/* Adjust the interface according to speed */
adjust_link(dev);
}
/* Initializes data structures and registers for the controller,
* and brings the interface up. Returns the link status, meaning
* that it returns success if the link is up, failure otherwise.
* This allows u-boot to find the first active controller.
*/
static int tsec_init(struct eth_device *dev, bd_t * bd)
{
uint tempval;
char tmpbuf[MAC_ADDR_LEN];
int i;
struct tsec_private *priv = (struct tsec_private *)dev->priv;
tsec_t *regs = priv->regs;
/* Make sure the controller is stopped */
tsec_halt(dev);
/* Init MACCFG2. Defaults to GMII */
out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
/* Init ECNTRL */
out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
/* Copy the station address into the address registers.
* Backwards, because little endian MACS are dumb */
for (i = 0; i < MAC_ADDR_LEN; i++)
tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
tmpbuf[3];
out_be32(®s->macstnaddr1, tempval);
tempval = *((uint *) (tmpbuf + 4));
out_be32(®s->macstnaddr2, tempval);
/* Clear out (for the most part) the other registers */
init_registers(regs);
/* Ready the device for tx/rx */
startup_tsec(dev);
/* Start up the PHY */
phy_startup(priv->phydev);
adjust_link(priv, priv->phydev);
/* If there's no link, fail */
return priv->phydev->link ? 0 : -1;
}
static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
uec_t *uec_regs;
int result = 0;
uec_regs = uec->uec_regs;
/* Delay 5s to give the PHY a chance to change the register state */
udelay(5000000);
/* Update the link, speed, duplex */
result = uec->mii_info->phyinfo->read_status(uec->mii_info);
/* Adjust the interface according to speed */
if ((0 == result) || (uec->mii_info->link == 0)) {
adjust_link(dev);
}
}
static int uec_init(struct eth_device* dev, bd_t *bd)
{
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
err = init_phy(dev);
if (err) {
printf("%s: Cannot initialize PHY, aborting.\n",
dev->name);
return err;
}
curphy = uec->mii_info->phyinfo;
if (curphy->config_aneg) {
err = curphy->config_aneg(uec->mii_info);
if (err) {
printf("%s: Can't negotiate PHY\n", dev->name);
return err;
}
}
/* Give PHYs up to 5 sec to report a link */
i = 50;
do {
err = curphy->read_status(uec->mii_info);
if (!(((i-- > 0) && !uec->mii_info->link) || err))
break;
udelay(100000);
} while (1);
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
/* QE12 needs to be released for enabling LBCTL signal*/
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif
if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name);
adjust_link(dev);
uec->the_first_run = 1;
}
/* Set up the MAC address */
if (dev->enetaddr[0] & 0x01) {
printf("%s: MacAddress is multcast address\n",
__FUNCTION__);
return -1;
}
uec_set_mac_address(uec, dev->enetaddr);
err = uec_open(uec, COMM_DIR_RX_AND_TX);
if (err) {
printf("%s: cannot enable UEC device\n", dev->name);
return -1;
}
phy_change(dev);
return (uec->mii_info->link ? 0 : -1);
}
static int uec_init(struct eth_device* dev, bd_t *bd)
{
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
err = init_phy(dev);
if (err) {
printf("%s: Cannot initialize PHY, aborting.\n",
dev->name);
return err;
}
curphy = uec->mii_info->phyinfo;
if (curphy->config_aneg) {
err = curphy->config_aneg(uec->mii_info);
if (err) {
printf("%s: Can't negotiate PHY\n", dev->name);
return err;
}
}
/* Give PHYs up to 5 sec to report a link */
i = 50;
do {
err = curphy->read_status(uec->mii_info);
if (!(((i-- > 0) && !uec->mii_info->link) || err))
break;
udelay(100000);
} while (1);
if (err || i <= 0)
printf("warning: %s: timeout on PHY link\n", dev->name);
adjust_link(dev);
uec->the_first_run = 1;
}
/* Set up the MAC address */
if (dev->enetaddr[0] & 0x01) {
printf("%s: MacAddress is multcast address\n",
__FUNCTION__);
return -1;
}
uec_set_mac_address(uec, dev->enetaddr);
err = uec_open(uec, COMM_DIR_RX_AND_TX);
if (err) {
printf("%s: cannot enable UEC device\n", dev->name);
return -1;
}
phy_change(dev);
return (uec->mii_info->link ? 0 : -1);
}
int
ndi_ra_alloc(dev_info_t *dip, ndi_ra_request_t *req, uint64_t *retbasep,
uint64_t *retlenp, char *type, uint32_t flag)
{
struct ra_dip_type *dipmap;
struct ra_resource *mapp, **backp, **backlargestp;
uint64_t mask = 0;
uint64_t len, remlen, largestbase, largestlen;
uint64_t base, oldbase, lower, upper;
struct ra_dip_type **backdip;
struct ra_type_map **backtype;
int rval = NDI_FAILURE;
len = req->ra_len;
if (req->ra_flags & NDI_RA_ALIGN_SIZE) {
if (isnot_pow2(req->ra_len)) {
DEBUGPRT(CE_WARN, "ndi_ra_alloc: bad length(pow2) 0x%"
PRIx64, req->ra_len);
*retbasep = 0;
*retlenp = 0;
return (NDI_FAILURE);
}
}
mask = (req->ra_flags & NDI_RA_ALIGN_SIZE) ? (len - 1) :
req->ra_align_mask;
mutex_enter(&ra_lock);
dipmap = find_dip_map_resources(dip, type, &backdip, &backtype, flag);
if ((dipmap == NULL) || ((mapp = dipmap->ra_rangeset) == NULL)) {
mutex_exit(&ra_lock);
DEBUGPRT(CE_CONT, "ndi_ra_alloc no map found for this type\n");
return (NDI_FAILURE);
}
DEBUGPRT(CE_CONT, "ndi_ra_alloc: mapp = %p len=%" PRIx64 ", mask=%"
PRIx64 "\n", (void *)mapp, len, mask);
backp = &(dipmap->ra_rangeset);
backlargestp = NULL;
largestbase = 0;
largestlen = 0;
lower = 0;
upper = ~(uint64_t)0;
if (req->ra_flags & NDI_RA_ALLOC_BOUNDED) {
/* bounded so skip to first possible */
lower = req->ra_boundbase;
upper = req->ra_boundlen + lower;
if ((upper == 0) || (upper < req->ra_boundlen))
upper = ~(uint64_t)0;
DEBUGPRT(CE_CONT, "ndi_ra_alloc: ra_len = %" PRIx64 ", len = %"
PRIx64 " ra_base=%" PRIx64 ", mask=%" PRIx64
"\n", mapp->ra_len, len, mapp->ra_base, mask);
for (; mapp != NULL &&
(mapp->ra_base + mapp->ra_len) < lower;
backp = &(mapp->ra_next), mapp = mapp->ra_next) {
if (((mapp->ra_len + mapp->ra_base) == 0) ||
((mapp->ra_len + mapp->ra_base) < mapp->ra_len))
/*
* This elements end goes beyond max uint64_t.
* potential candidate, check end against lower
* would not be precise.
*/
break;
DEBUGPRT(CE_CONT, " ra_len = %" PRIx64 ", ra_base=%"
PRIx64 "\n", mapp->ra_len, mapp->ra_base);
}
}
if (!(req->ra_flags & NDI_RA_ALLOC_SPECIFIED)) {
/* first fit - not user specified */
DEBUGPRT(CE_CONT, "ndi_ra_alloc(unspecified request)"
"lower=%" PRIx64 ", upper=%" PRIx64 "\n", lower, upper);
for (; mapp != NULL && mapp->ra_base <= upper;
backp = &(mapp->ra_next), mapp = mapp->ra_next) {
DEBUGPRT(CE_CONT, "ndi_ra_alloc: ra_len = %" PRIx64
", len = %" PRIx64 "", mapp->ra_len, len);
base = mapp->ra_base;
if (base < lower) {
base = lower;
DEBUGPRT(CE_CONT, "\tbase=%" PRIx64
", ra_base=%" PRIx64 ", mask=%" PRIx64,
base, mapp->ra_base, mask);
}
if ((base & mask) != 0) {
oldbase = base;
/*
* failed a critical constraint
* adjust and see if it still fits
*/
base = base & ~mask;
base += (mask + 1);
DEBUGPRT(CE_CONT, "\tnew base=%" PRIx64 "\n",
base);
/*
* Check to see if the new base is past
* the end of the resource.
*/
if (base >= (oldbase + mapp->ra_len + 1)) {
continue;
}
}
if (req->ra_flags & NDI_RA_ALLOC_PARTIAL_OK) {
if ((upper - mapp->ra_base) < mapp->ra_len)
remlen = upper - base;
else
remlen = mapp->ra_len -
(base - mapp->ra_base);
if ((backlargestp == NULL) ||
(largestlen < remlen)) {
backlargestp = backp;
largestbase = base;
largestlen = remlen;
}
}
if (mapp->ra_len >= len) {
/* a candidate -- apply constraints */
if ((len > (mapp->ra_len -
(base - mapp->ra_base))) ||
((len - 1 + base) > upper)) {
continue;
}
/* we have a fit */
DEBUGPRT(CE_CONT, "\thave a fit\n");
adjust_link(backp, mapp, base, len);
rval = NDI_SUCCESS;
break;
}
}
} else {
/* want an exact value/fit */
base = req->ra_addr;
len = req->ra_len;
for (; mapp != NULL && mapp->ra_base <= upper;
backp = &(mapp->ra_next), mapp = mapp->ra_next) {
if (base >= mapp->ra_base &&
((base - mapp->ra_base) < mapp->ra_len)) {
/*
* This is the node with he requested base in
* its range
*/
if ((len > mapp->ra_len) ||
(base - mapp->ra_base >
mapp->ra_len - len)) {
/* length requirement not satisfied */
if (req->ra_flags &
NDI_RA_ALLOC_PARTIAL_OK) {
if ((upper - mapp->ra_base)
< mapp->ra_len)
remlen = upper - base;
else
remlen =
mapp->ra_len -
(base -
mapp->ra_base);
}
backlargestp = backp;
largestbase = base;
largestlen = remlen;
base = 0;
} else {
/* We have a match */
adjust_link(backp, mapp, base, len);
rval = NDI_SUCCESS;
}
break;
}
}
}
if ((rval != NDI_SUCCESS) &&
(req->ra_flags & NDI_RA_ALLOC_PARTIAL_OK) &&
(backlargestp != NULL)) {
adjust_link(backlargestp, *backlargestp, largestbase,
largestlen);
base = largestbase;
len = largestlen;
rval = NDI_RA_PARTIAL_REQ;
}
mutex_exit(&ra_lock);
if (rval == NDI_FAILURE) {
*retbasep = 0;
*retlenp = 0;
} else {
*retbasep = base;
*retlenp = len;
}
return (rval);
}
