int stm32_adc_setup(void) { static bool initialized = false; uint8_t channel[1] = {10}; struct adc_dev_s *adc; int rv; if (initialized) { return OK; } ainfo("INFO: Initializing ADC12_IN10\n"); stm32_configgpio(GPIO_ADC12_IN10); if ((adc = stm32_adcinitialize(1, channel, 1)) == NULL) { aerr("ERROR: Failed to get adc interface\n"); return -ENODEV; } if ((rv = adc_register("/dev/adc0", adc)) < 0) { aerr("ERROR: adc_register failed: %d\n", rv); return rv; } initialized = true; ainfo("INFO: ADC12_IN10 initialized succesfully\n"); return OK; }
static void tiva_adc_runtimeobj_vals(void) { struct tiva_adc_sse_s *sse; uint8_t s; # ifdef CONFIG_TIVA_ADC0 ainfo("ADC0 [0x%08x] cfg=%d ena=%d devno=%d\n", &adc0, adc0.cfg, adc0.ena, adc0.devno); for (s = 0; s < 4; ++s) { sse = g_sses[SSE_IDX(0, s)]; ainfo("SSE%d [0x%08x] adc=%d cfg=%d ena=%d num=%d\n", s, sse, sse->adc, sse->cfg, sse->ena, sse->num); } # endif # ifdef CONFIG_TIVA_ADC1 ainfo("ADC1 [0x%08x] cfg=%d ena=%d devno=%d\n", &adc1, adc1.cfg, adc1.ena, adc1.devno); for (s = 0; s < 4; ++s) { sse = g_sses[SSE_IDX(1, s)]; ainfo("SSE%d [0x%08x] adc=%d cfg=%d ena=%d num=%d\n", s, sse, sse->adc, sse->cfg, sse->ena, sse->num); } # endif }
void tiva_adc_configure(struct tiva_adc_cfg_s *cfg) { uint8_t s; uint8_t c; ainfo("configure ADC%d...\n", cfg->adc); /* Configure each SSE */ for (s = 0; s < 4; ++s) { if (cfg->sse[s]) { tiva_adc_sse_cfg(cfg->adc, s, &cfg->ssecfg[s]); } #ifdef CONFIG_DEBUG_ANALOG else { ainfo("ADC%d SSE%d has no configuration\n", cfg->adc, s); } #endif } /* Configure each step */ for (c = 0; c < cfg->steps; ++c) { tiva_adc_step_cfg(&cfg->stepcfg[c]); } #ifdef CONFIG_DEBUG_ANALOG tiva_adc_dump_reg_cfg(cfg->adc, 0); #endif }
void tiva_adc_lock(FAR struct tiva_adc_s *priv, int sse) { struct tiva_adc_sse_s *s = g_sses[SSE_IDX(priv->devno, sse)]; int ret; #ifdef CONFIG_DEBUG_ANALOG uint16_t loop_count = 0; #endif ainfo("Locking...\n"); do { ret = nxsem_wait(&s->exclsem); /* This should only fail if the wait was canceled by an signal (and the * worker thread will receive a lot of signals). */ DEBUGASSERT(ret == OK || ret == -EINTR); #ifdef CONFIG_DEBUG_ANALOG if (loop_count % 1000) { ainfo("loop=%d\n"); } ++loop_count; #endif } while (ret == -EINTR); }
FAR struct dac_dev_s *stm32_dacinitialize(int intf) { FAR struct dac_dev_s *dev; FAR struct stm32_chan_s *chan; int ret; #ifdef CONFIG_STM32_DAC1 if (intf == 1) { ainfo("DAC1-1 Selected\n"); dev = &g_dac1dev; } else if (intf == 2) { ainfo("DAC1-2 Selected\n"); dev = &g_dac2dev; } else #endif #ifdef CONFIG_STM32_DAC2 if (intf == 3) { ainfo("DAC2-1 Selected\n"); dev = &g_dac3dev; } else #endif { aerr("ERROR: No such DAC interface: %d\n", intf); errno = ENODEV; return NULL; } /* Make sure that the DAC block has been initialized */ ret = dac_blockinit(); if (ret < 0) { aerr("ERROR: Failed to initialize the DAC block: %d\n", ret); errno = -ret; return NULL; } /* Configure the selected DAC channel */ chan = dev->ad_priv; ret = dac_chaninit(chan); if (ret < 0) { aerr("ERROR: Failed to initialize DAC channel %d: %d\n", intf, ret); errno = -ret; return NULL; } return dev; }
static void tiva_adc_dump_dev(void) { # ifdef CONFIG_TIVA_ADC0 ainfo("adc_ops_s g_adcops=0x%08x adc0.dev->ad_ops=0x%08x\n", &g_adcops, adc0.dev->ad_ops); ainfo("tiva_adc_s adc0=0x%08x adc0.dev->ad_priv=0x%08x\n", &adc0, adc0.dev->ad_priv); # endif # ifdef CONFIG_TIVA_ADC1 ainfo("adc_ops_s g_adcops=0x%08x adc1.dev->ad_ops=0x%08x\n", &g_adcops, adc1.dev->ad_ops); ainfo("tiva_adc_s adc1=0x%08x adc1.dev->ad_priv=0x%08x\n", &adc1, adc1.dev->ad_priv); # endif }
static void tiva_adc_read(void *arg) { struct tiva_adc_s *priv; struct tiva_adc_sse_s *sse = (struct tiva_adc_sse_s *)arg; struct adc_dev_s *dev = 0; int irq = tiva_adc_getirq(sse->adc, sse->num); uint8_t i = 0; uint8_t fifo_count = 0; int32_t buf[8]; /* Get exclusive access to the driver data structure */ tiva_adc_lock(g_adcs[sse->adc], sse->num); /* Get sampled data */ fifo_count = tiva_adc_sse_data(sse->adc, sse->num, buf); /* Determine which adc_dev_s we need */ dev = g_devs[sse->adc]; if (dev == NULL) { /* This is a serious error: indicates invalid pointer indirection * and should cause a full system stop. */ aerr("ERROR: Invalid ADC device number given %d\n", sse->adc); DEBUGPANIC(); return; } priv = (struct tiva_adc_s *)dev->ad_priv; /* Verify that the upper-half driver has bound its callback functions */ if (priv->cb != NULL) { DEBUGASSERT(priv->cb->au_receive != NULL); for (i = 0; i < fifo_count; ++i) { /* Perform the data received callback */ priv->cb->au_receive(dev, tiva_adc_get_ain(sse->adc, sse->num, i), buf[i]); ainfo("AIN%d = 0x%04x\n", tiva_adc_get_ain(sse->adc, sse->num, i), buf[i]); } } /* Exit, re-enabling ADC interrupts */ up_enable_irq(irq); /* Release our lock on the ADC structure */ tiva_adc_unlock(g_adcs[sse->adc], sse->num); }
void tiva_adc_sse_cfg(uint8_t adc, uint8_t sse, struct tiva_adc_sse_cfg_s *ssecfg) { uint8_t priority = ssecfg->priority; uint8_t trigger = ssecfg->trigger; ainfo("configure ADC%d SSE%d...\n", adc, sse); #ifdef CONFIG_DEBUG_ANALOG ainfo("priority=%d trigger=%d...\n", ssecfg->priority, ssecfg->trigger); #endif /* Ensure SSE is disabled before configuring */ tiva_adc_sse_enable(adc, sse, false); /* Set conversion priority and trigger source for all steps in the SSE */ tiva_adc_sse_priority(adc, sse, priority); tiva_adc_sse_trigger(adc, sse, trigger); }
int lc823450_wm8776initialize(int minor) { FAR struct audio_lowerhalf_s *wm8776; FAR struct audio_lowerhalf_s *pcm; FAR struct i2c_master_s *i2c; FAR struct i2s_dev_s *i2s; char devname[12]; int ret; ainfo("Initializing WM8776 \n"); /* Initialize I2C */ i2c = lc823450_i2cbus_initialize(WM8776_I2C_PORTNO); if (!i2c) { return -ENODEV; } i2s = lc823450_i2sdev_initialize(); #ifdef CONFIG_AUDIO_I2SCHAR i2schar_register(i2s, 0); #endif wm8776 = wm8776_initialize(i2c, i2s, &g_wm8776info); if (!wm8776) { auderr("ERROR: Failed to initialize the WM8904\n"); return -ENODEV; } pcm = pcm_decode_initialize(wm8776); if (!pcm) { auderr("ERROR: Failed create the PCM decoder\n"); return -ENODEV; } snprintf(devname, 12, "pcm%d", minor); ret = audio_register(devname, pcm); if (ret < 0) { auderr("ERROR: Failed to register /dev/%s device: %d\n", devname, ret); } return 0; }
static void tiva_adc_irqinitialize(struct tiva_adc_cfg_s *cfg) { ainfo("initialize irqs for ADC%d...\n", cfg->adc); #ifdef CONFIG_TIVA_ADC0 if (cfg->adc == 0) { if (cfg->sse[0] && (cfg->ssecfg[0].trigger > 0)) { tiva_adc_irq_attach(0, 0, tiva_adc0_sse0_interrupt); } if (cfg->sse[1] && (cfg->ssecfg[1].trigger > 0)) { tiva_adc_irq_attach(0, 1, tiva_adc0_sse1_interrupt); } if (cfg->sse[2] && (cfg->ssecfg[2].trigger > 0)) { tiva_adc_irq_attach(0, 2, tiva_adc0_sse2_interrupt); } if (cfg->sse[3] && (cfg->ssecfg[3].trigger > 0)) { tiva_adc_irq_attach(0, 3, tiva_adc0_sse3_interrupt); } } #endif #ifdef CONFIG_TIVA_ADC1 if (cfg->adc == 1) { if (cfg->sse[0] && (cfg->ssecfg[0].trigger > 0)) { tiva_adc_irq_attach(1, 0, tiva_adc1_sse0_interrupt); } if (cfg->sse[1] && (cfg->ssecfg[1].trigger > 0)) { tiva_adc_irq_attach(1, 1, tiva_adc1_sse1_interrupt); } if (cfg->sse[2] && (cfg->ssecfg[2].trigger > 0)) { tiva_adc_irq_attach(1, 2, tiva_adc1_sse2_interrupt); } if (cfg->sse[3] && (cfg->ssecfg[3].trigger > 0)) { tiva_adc_irq_attach(1, 3, tiva_adc1_sse3_interrupt); } } #endif }
void tiva_adc_one_time_init(uint32_t clock, uint8_t sample_rate) { static bool one_time_init = false; #ifdef CONFIG_DEBUG_ANALOG ainfo("setting clock=%d MHz sample rate=%d\n", clock, sample_rate); #endif /* Have the common peripheral properties already been initialized? If yes, * continue. */ if (one_time_init == false) { ainfo("performing ADC one-time initialization...\n"); /* Set clock */ tiva_adc_clock(clock); /* Set sampling rate */ tiva_adc_sample_rate(sample_rate); #ifdef CONFIG_ARCH_CHIP_TM4C129 /* Voltage reference */ tiva_adc_vref(INTERNAL_VREF); #endif one_time_init = true; } #ifdef CONFIG_DEBUG_ANALOG else { ainfo("one time initialization previously completed\n"); } #endif }
void tiva_adc_step_cfg(struct tiva_adc_step_cfg_s *stepcfg) { #ifdef CONFIG_DEBUG_ANALOG ainfo(" shold=0x%02x flags=0x%02x ain=%d...\n", stepcfg->shold, stepcfg->flags, stepcfg->ain); #endif uint8_t adc = stepcfg->adc; uint8_t sse = stepcfg->sse; uint8_t step = stepcfg->step; #ifdef CONFIG_EXPERIMENTAL uint8_t shold = stepcfg->shold; #endif uint8_t flags = stepcfg->flags; uint8_t ain = stepcfg->ain; uint32_t gpio = ain2gpio[stepcfg->ain]; ainfo("configure ADC%d SSE%d STEP%d...\n", adc, sse, step); /* Configure the AIN GPIO for analog input if not flagged to be muxed to * the internal temperature sensor */ if ((flags & TIVA_ADC_FLAG_TS) != TIVA_ADC_FLAG_TS) { tiva_configgpio(gpio); } /* Register, set sample/hold time and configure the step */ tiva_adc_sse_register_chn(adc, sse, step, ain); tiva_adc_sse_differential(adc, sse, step, 0); /* TODO: update when differential * support is added. */ #ifdef CONFIG_EXPERIMENTAL tiva_adc_sse_sample_hold_time(adc, sse, step, shold); #endif tiva_adc_sse_step_cfg(adc, sse, step, flags); }
uint8_t tiva_adc_sse_enable(uint8_t adc, uint8_t sse, bool state) { ainfo("ADC%d SSE%d=%01d\n", adc, sse, state); uintptr_t actssreg = TIVA_ADC_ACTSS(adc); if (state == true) { modifyreg32(actssreg, 0, (1 << sse)); } else { modifyreg32(actssreg, (1 << sse), 0); } return (getreg32(actssreg) & 0xF); }
void tiva_adc_irq_attach(uint8_t adc, uint8_t sse, xcpt_t isr) { uint32_t ret = 0; int irq = sse2irq[SSE_IDX(adc, sse)]; #ifdef CONFIG_DEBUG_ANALOG ainfo("assigning ISR=0x%p to ADC%d SSE%d IRQ=0x%02x...\n", isr, adc, sse, irq); #endif ret = irq_attach(irq, isr, NULL); if (ret < 0) { aerr("ERROR: Failed to attach IRQ %d: %d\n", irq, ret); return; } up_enable_irq(irq); }
static void tiva_adc_reset(struct adc_dev_s *dev) { struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv; struct tiva_adc_sse_s *sse; uint8_t s; ainfo("Resetting...\n"); tiva_adc_rxint(dev, false); for (s = 0; s < 4; ++s) { sse = g_sses[SSE_IDX(priv->devno, s)]; if (sse->ena == true) { tiva_adc_sse_enable(priv->devno, s, false); sse->ena = false; } } }
static void tiva_adc_rxint(struct adc_dev_s *dev, bool enable) { struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv; struct tiva_adc_sse_s *sse; uint32_t trigger; uint8_t s = 0; ainfo("RXINT=%d\n", enable); DEBUGASSERT(priv->ena); for (s = 0; s < 4; ++s) { trigger = tiva_adc_get_trigger(priv->devno, s); sse = g_sses[SSE_IDX(priv->devno, s)]; if ((sse->ena == true) && (trigger > 0)) { tiva_adc_sse_int_enable(priv->devno, s, enable); } } }
uint8_t tiva_adc_sse_data(uint8_t adc, uint8_t sse, int32_t *buf) { uint32_t ssfstatreg = getreg32(TIVA_ADC_BASE(adc) + TIVA_ADC_SSFSTAT(sse)); uint8_t fifo_count = 0; /* Read samples from the FIFO until it is empty */ while (!(ssfstatreg & ADC_SSFSTAT_EMPTY) && fifo_count < 8) { /* Read the FIFO and copy it to the destination */ buf[fifo_count] = getreg32(TIVA_ADC_BASE(adc) + TIVA_ADC_SSFIFO(sse)); fifo_count++; /* refresh fifo status register state */ ssfstatreg = getreg32(TIVA_ADC_BASE(adc) + TIVA_ADC_SSFSTAT(sse)); } ainfo("fifo=%d\n", fifo_count); return fifo_count; }
static int tiva_adc_setup(struct adc_dev_s *dev) { struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv; struct tiva_adc_sse_s *sse; uint8_t s = 0; ainfo("Setup\n"); priv->ena = true; for (s = 0; s < 4; ++s) { sse = g_sses[SSE_IDX(priv->devno, s)]; if (sse->cfg == true) { tiva_adc_sse_enable(priv->devno, s, true); sse->ena = true; } } tiva_adc_rxint(dev, false); return OK; }
static void tiva_adc_shutdown(struct adc_dev_s *dev) { struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv; ainfo("Shutdown\n"); DEBUGASSERT(priv->ena); /* Resetting the ADC peripheral disables interrupts and all SSEs */ tiva_adc_reset(dev); /* Currently all of the setup operations are undone in reset() */ #if 0 struct tiva_adc_sse_s *sse; uint8_t s = 0; for (s = 0; s < 4; ++s) { } #endif priv->ena = false; }
void tiva_adc_dump_reg_cfg(uint8_t adc, uint8_t sse) { /* one-time initialization */ uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET); /* Clock */ uintptr_t pcreg = (TIVA_ADC0_BASE + TIVA_ADC_PC_OFFSET); /* Sample rate */ /* SSE cfg */ uintptr_t actssreg = TIVA_ADC_ACTSS(adc); /* SSE enable state */ uintptr_t ssprireg = TIVA_ADC_SSPRI(adc); /* SSE priority */ uintptr_t emuxreg = TIVA_ADC_EMUX(adc); /* SSE trigger */ /* step cfg */ uintptr_t ssmuxreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSMUX(sse)); /* step registration */ #ifdef CONFIG_ARCH_CHIP_TM4C129 uintptr_t ssemuxreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSEMUX(sse)); /* extended mux registration */ #endif uintptr_t ssopreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSOP(sse)); /* differential status */ #ifdef CONFIG_EXPERIMENTAL uintptr_t sstshreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSTSH(sse)); /* sample and hold time */ #endif uintptr_t ssctlreg = (TIVA_ADC_BASE(adc) + TIVA_ADC_SSCTL(sse)); /* step configuration */ /* Get register contents */ uint32_t cc = getreg32(ccreg); uint32_t pc = getreg32(pcreg); /* SSE cfg */ uint32_t actss = getreg32(actssreg); uint32_t sspri = getreg32(ssprireg); uint32_t emux = getreg32(emuxreg); /* step cfg */ uint32_t ssmux = getreg32(ssmuxreg); #ifdef CONFIG_ARCH_CHIP_TM4C129 uint32_t ssemux = getreg32(ssemuxreg); #endif uint32_t ssop = getreg32(ssopreg); #ifdef CONFIG_EXPERIMENTAL uint32_t sstsh = getreg32(sstshreg); #endif uint32_t ssctl = getreg32(ssctlreg); /* Dump register contents */ ainfo("CC [0x%08x]=0x%08x\n", ccreg, cc); ainfo("PC [0x%08x]=0x%08x\n", pcreg, pc); ainfo("ACTSS [0x%08x]=0x%08x\n", actssreg, actss); ainfo("SSPRI [0x%08x]=0x%08x\n", ssprireg, sspri); ainfo("EMUX [0x%08x]=0x%08x\n", emuxreg, emux); ainfo("SSMUX [0x%08x]=0x%08x\n", ssmuxreg, ssmux); #ifdef CONFIG_ARCH_CHIP_TM4C129 ainfo("SSEMUX [0x%08x]=0x%08x\n", ssemuxreg, ssemux); #endif ainfo("SSOP [0x%08x]=0x%08x\n", ssopreg, ssop); #ifdef CONFIG_EXPERIMENTAL ainfo("SSTSH [0x%08x]=0x%08x\n", sstshreg, sstsh); #endif ainfo("SSCTL [0x%08x]=0x%08x\n", ssctlreg, ssctl); }
void MvcBook::UpdateTitle() { MvcView* pView=m_pBook->m_pActiveView; if(!pView) return; ViewInfo& vinfo(m_aOpenedViews[pView]); String title = pView->GetTitle(); if (vinfo.title != title) { vinfo.title = title; vinfo.index = -1; } vinfo.dirty=pView->Target.TestId(CmdProc::CP_DIRTY); class MyViewInfoLess { public: bool operator()(ViewInfo* lhs, ViewInfo* rhs) { if (lhs->index < rhs->index) return true; if (lhs->index > rhs->index) return false; return lhs->timestamp < rhs->timestamp; } }; bst_map<String, bst_set<ViewInfo*, MyViewInfoLess> > ainfo; for (auto it = m_aOpenedViews.begin(); it != m_aOpenedViews.end(); ++it) { ainfo[(*it).second.title].insert(&(*it).second); } for (auto it = ainfo.begin(); it != ainfo.end(); it++) { bst_set<ViewInfo*, MyViewInfoLess>& ainfo((*it).second); if (ainfo.size() == 1) { (*ainfo.begin())->index = -1; continue; } int n = (*ainfo.rbegin())->index; for (auto it = ainfo.begin(); it != ainfo.end() && (*it)->index < 0; ++it) { (*it)->index = ++n; } } for (view_map::iterator it = m_aOpenedViews.begin(); it != m_aOpenedViews.end(); ++it) { ViewInfo& vinfo((*it).second); String title; if (vinfo.dirty) title << "* "; else title << " "; title << vinfo.title; if (vinfo.index >= 0) { title << ":" << vinfo.index; } if (title == vinfo.title_n) continue; vinfo.title_n = title; wxWindow* pCanvas = (*it).first->GetCanvas(); int id = m_pBook->GetPageIndex(pCanvas); if (id >= 0) { m_pBook->SetPageText(id, str2wx(title)); } else { System::LogTrace("canvas not found"); } } }
int tiva_adc_initialize(const char *devpath, struct tiva_adc_cfg_s *cfg, uint32_t clock, uint8_t sample_rate) { struct tiva_adc_s *adc; int ret = 0; ainfo("initializing...\n"); /* Initialize the private ADC device data structure */ adc = tiva_adc_struct_init(cfg); if (adc == NULL) { aerr("ERROR: Invalid ADC device number: expected=%d actual=%d\n", 0, cfg->adc); return -ENODEV; } /* Turn on peripheral */ if (tiva_adc_enable(adc->devno, true) < 0) { aerr("ERROR: failure to power ADC peripheral (devno=%d)\n", cfg->adc); return ret; } /* Perform actual initialization */ tiva_adc_one_time_init(clock, sample_rate); tiva_adc_configure(cfg); tiva_adc_irqinitialize(cfg); /* Now we are initialized */ adc->ena = true; adc->cb = NULL; #ifdef CONFIG_DEBUG_ANALOG tiva_adc_runtimeobj_vals(); #endif /* Ensure our lower half is valid */ if (adc->dev == NULL) { aerr("ERROR: Failed to get interface %s\n", devpath); return -ENODEV; } ainfo("adc_dev_s=0x%08x\n", adc->dev); /* Register the ADC driver */ ainfo("Register the ADC driver at %s\n", devpath); ret = adc_register(devpath, adc->dev); if (ret < 0) { aerr("ERROR: Failed to register %s to character driver: %d\n", devpath, ret); return ret; } return OK; }
static struct tiva_adc_s *tiva_adc_struct_init(struct tiva_adc_cfg_s *cfg) { struct tiva_adc_s *adc = g_adcs[cfg->adc]; struct tiva_adc_sse_s *sse = 0; uint8_t s = 0; /* Do not re-initialize the run-time structures, there is a chance another * process is also using this ADC. */ if (adc->cfg == true) { goto tiva_adc_struct_init_ok; } else { if (adc != NULL) { adc->ena = false; adc->devno = cfg->adc; for (s = 0; s < 4; s++) { /* Only configure selected SSEs */ if (cfg->sse[s]) { sse = g_sses[SSE_IDX(cfg->adc, s)]; if (sse != NULL) { sse->adc = cfg->adc; sse->num = s; nxsem_init(&sse->exclsem, SEM_PROCESS_PRIVATE, 1); sse->ena = false; sse->cfg = true; } else { goto tiva_adc_struct_init_error; } } } /* Initialize the public ADC device data structure */ adc->dev = g_devs[cfg->adc]; if (adc->dev != NULL) { adc->dev->ad_ops = &g_adcops; adc->dev->ad_priv = adc; } else { goto tiva_adc_struct_init_error; } goto tiva_adc_struct_init_ok; } else { goto tiva_adc_struct_init_error; } } tiva_adc_struct_init_error: ainfo("Invalid ADC device number: expected=%d actual=%d\n", 0, cfg->adc); ainfo("ADC%d (CONFIG_TIVA_ADC%d) must be enabled in Kconfig first!", cfg->adc, cfg->adc); return NULL; tiva_adc_struct_init_ok: adc->cfg = true; return adc; }
static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) { int ret = OK; ainfo("cmd=%d arg=%ld\n", cmd, arg); switch (cmd) { /* Software trigger */ case ANIOC_TRIGGER: { struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv; uint8_t i = 0; uint8_t fifo_count = 0; uint8_t sse = (uint8_t) arg; int32_t buf[8]; /* Get exclusive access to the driver data structure */ tiva_adc_lock(priv, sse); /* Start conversion and wait for end of conversion */ tiva_adc_proc_trig(priv->devno, (uint8_t)SSE_PROC_TRIG(sse)); while (!tiva_adc_sse_int_status(priv->devno, sse)) { nxsig_usleep(100); } tiva_adc_sse_clear_int(priv->devno, sse); /* Pass sampled data to upper ADC driver */ fifo_count = tiva_adc_sse_data(priv->devno, sse, buf); /* Verify that the upper-half driver has bound its callback functions */ if (priv->cb != NULL) { DEBUGASSERT(priv->cb->au_receive != NULL); for (i = 0; i < fifo_count; ++i) { /* Perform the data received callback */ priv->cb->au_receive(dev, tiva_adc_get_ain(priv->devno, sse, i), buf[i]); } } /* Release our lock on the ADC structure */ tiva_adc_unlock(priv, sse); } break; /* PWM triggering */ #warning Missing Logic /* TODO: Needs to be tested */ #ifdef CONFIG_EXPERIMENTAL case TIVA_ADC_PWM_TRIG_IOCTL: { uint8_t sse = (uint8_t)(arg & 0x2); uint8_t regval = tiva_adc_get_trigger(adc, sse); /* Verify input SSE trigger is a PWM trigger */ if ((regval & TIVA_ADC_TRIG_PWM0) || (regval & TIVA_ADC_TRIG_PWM1) || (regval & TIVA_ADC_TRIG_PWM2) || (regval & TIVA_ADC_TRIG_PWM3)) { tiva_adc_sse_pwm_trig(adc, sse, (uint32_t)(arg&0xFFFFFFFC)); } } break; #endif #warning Missing Logic /* Unsupported or invalid command */ default: ret = -ENOTTY; break; } return ret; }
void tiva_adc_unlock(FAR struct tiva_adc_s *priv, int sse) { struct tiva_adc_sse_s *s = g_sses[SSE_IDX(priv->devno, sse)]; ainfo("Unlocking\n"); nxsem_post(&s->exclsem); }
static void tiva_adc_runtimeobj_ptrs(void) { # ifdef CONFIG_TIVA_ADC0 ainfo("ADC0 [struct] [global value] [array value]\n"); ainfo(" adc_dev_s dev0=0x%08x g_devs[0]=0x%08x\n", &dev0, g_devs[0]); ainfo(" tiva_adc_s adc0=0x%08x g_adcs[0]=0x%08x\n", &adc0, g_adcs[0]); ainfo(" tiva_adc_sse_s sse0=0x%08x g_sses[0,0]=0x%08x\n", &sse00, g_sses[SSE_IDX(0, 0)]); ainfo(" tiva_adc_sse_s sse1=0x%08x g_sses[0,1]=0x%08x\n", &sse01, g_sses[SSE_IDX(0, 1)]); ainfo(" tiva_adc_sse_s sse2=0x%08x g_sses[0,2]=0x%08x\n", &sse02, g_sses[SSE_IDX(0, 2)]); ainfo(" tiva_adc_sse_s sse3=0x%08x g_sses[0,3]=0x%08x\n", &sse03, g_sses[SSE_IDX(0, 3)]); # endif # ifdef CONFIG_TIVA_ADC1 ainfo("ADC1 [struct] [global value] [array value]\n"); ainfo(" adc_dev_s dev1=0x%08x g_devs[1]=0x%08x\n", &dev1, g_devs[1]); ainfo(" tiva_adc_s adc1=0x%08x g_adcs[1]=0x%08x\n", &adc1, g_adcs[1]); ainfo(" tiva_adc_sse_s sse0=0x%08x g_sses[1,0]=0x%08x\n", &sse10, g_sses[SSE_IDX(1, 0)]); ainfo(" tiva_adc_sse_s sse1=0x%08x g_sses[1,1]=0x%08x\n", &sse11, g_sses[SSE_IDX(1, 1)]); ainfo(" tiva_adc_sse_s sse2=0x%08x g_sses[1,2]=0x%08x\n", &sse12, g_sses[SSE_IDX(1, 2)]); ainfo(" tiva_adc_sse_s sse3=0x%08x g_sses[1,3]=0x%08x\n", &sse13, g_sses[SSE_IDX(1, 3)]); # endif }