int *new_int_vector(int n)
{
int *v = NULL;
v = alloc_int_vector(n);
return v;
}
void init_ioapic()
{
ulong ioapic_paddr = IOAPIC_DEFAULT_PADDR;
ulong ioapic_vaddr = IOAPIC_TOP_VADDR;
ioapic_count = 8;
if (acpi_supported && madt_supported) {
kprintf("acpi supported!\n");
if (madt_ioapic_count < ioapic_count) {
ioapic_count = madt_ioapic_count;
}
assert(ioapic_count > 0);
struct acpi_madt_ioapic *e = NULL;
int i = 0;
while ((e = get_next_acpi_ioapic_entry(e, &ioapic_paddr)) != NULL) {
assert(ioapic_paddr);
ioapic_vaddr -= PAGE_SIZE;
kernel_indirect_map_array(
ioapic_vaddr, ioapic_paddr, PAGE_SIZE, 1, 1
);
kprintf("\tIOAPIC #%d mapped: %p -> %p\n", i, ioapic_vaddr, ioapic_paddr);
i++;
}
}
else if (mps_supported) {
if (mps_ioapic_count < ioapic_count) {
ioapic_count = mps_ioapic_count;
}
assert(ioapic_count > 0);
struct mps_ioapic *e = NULL;
int i = 0;
while ((e = get_next_mps_ioapic_entry(e, &ioapic_paddr)) != NULL) {
assert(ioapic_paddr);
ioapic_vaddr -= PAGE_SIZE;
kernel_indirect_map_array(
ioapic_vaddr, ioapic_paddr, PAGE_SIZE, 1, 1
);
kprintf("\tIOAPIC #%d mapped: %p -> %p\n", i, ioapic_vaddr, ioapic_paddr);
i++;
}
}
// Update HAL virtual space boundary
get_bootparam()->hal_vspace_end -= PAGE_SIZE * ioapic_count;
//panic("get_bootparam()->hal_vspace_end: %p\n", get_bootparam()->hal_vspace_end);
// Override IO APIC using MADT or MPS
int i;
// Set default ISA IRQ map
for (i = 0; i < 16; i++) {
irq_map[i].chip = 0;
irq_map[i].pin = i;
irq_map[i].irq = i;
irq_map[i].vector = i;
irq_map[i].available = 1;
// Default ISA Trigger Mode: EDGE (As ACPI Specification 5.0)
irq_map[i].trigger = APIC_TRIGMOD_EDGE;
// Default ISA Polarity: Active High (I guess)
irq_map[i].polarity = APIC_POLARITY_HIGH;
}
if (acpi_supported && madt_supported) {
// Go through MADT Interrupt Structures
ioapic_override_madt();
} else if (mps_supported) {
// Go through MP IO Interrupt Structures
ioapic_override_mps();
}
kprintf("\tIO APIC IRQ map\n");
for (i = 0; i < 16; i++) {
if (!irq_map[i].available) {
continue;
}
kprintf("\t\tIRQ: %d, Chip: %d, Pin: %d, Trigger: %d, Polarity: %d\n",
irq_map[i].irq,
irq_map[i].chip,
irq_map[i].pin,
irq_map[i].trigger,
irq_map[i].polarity
);
}
kprintf("\tIO APIC vector map\n");
// Initialize Vector Map
for (i = 0; i < 256; i++) {
vector_map[i].available = 0;
}
// Generate Vector Map, and Program Redirection Table
for (i = 0; i < 256; i++) {
if (!irq_map[i].available) {
continue;
}
int vector = alloc_int_vector(ioapic_handler);
vector_map[vector].vector = vector;
vector_map[vector].irq = irq_map[i].irq;
vector_map[vector].chip = irq_map[i].chip;
vector_map[vector].pin = irq_map[i].pin;
vector_map[vector].available = irq_map[i].available;
vector_map[vector].trigger = irq_map[i].trigger;
vector_map[vector].polarity = irq_map[i].polarity;
// if (irq_map[i].irq >= 2) {
// continue;
// }
// Redirection Table
ioapic_init_redirection_table(
vector_map[vector].chip,
vector_map[vector].pin,
vector,
vector_map[vector].trigger,
vector_map[vector].polarity
);
kprintf("\t\tVector: %d, IRQ: %d, Chip: %d, Pin: %d, Trigger: %d, Polarity: %d\n",
vector,
vector_map[vector].irq,
vector_map[vector].chip,
vector_map[vector].pin,
vector_map[vector].trigger,
vector_map[vector].polarity
);
}
//panic("here");
}
