/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
static noinline void pcm051_board_init(void)
{
unsigned long sdram = 0x80000000, fdt;
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
&MT41J256M8HX15E_2x256M8_regs,
&MT41J256M8HX15E_2x256M8_data);
am33xx_uart0_soft_reset();
am33xx_enable_uart0_pin_mux();
omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
putc_ll('>');
/*
* Copy the devicetree blob to sdram so that the barebox code finds it
* inside valid SDRAM instead of SRAM.
*/
memcpy((void *)sdram, __dtb_am335x_phytec_phycore_start,
__dtb_am335x_phytec_phycore_end -
__dtb_am335x_phytec_phycore_start);
fdt = sdram;
barebox_arm_entry(sdram, SZ_512M, fdt);
}
/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
static noinline void pcm051_board_init(void)
{
void *fdt;
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while (readl(AM33XX_WDT_REG(WWPS)) != 0x0);
am33xx_pll_init(MPUPLL_M_600, 25, DDRPLL_M_303);
am335x_sdram_init(0x18B, &MT41J256M8HX15E_2x256M8_cmd,
&MT41J256M8HX15E_2x256M8_regs,
&MT41J256M8HX15E_2x256M8_data);
am33xx_uart0_soft_reset();
am33xx_enable_uart0_pin_mux();
omap_uart_lowlevel_init((void *)AM33XX_UART0_BASE);
putc_ll('>');
fdt = __dtb_am335x_phytec_phycore_start - get_runtime_offset();
barebox_arm_entry(0x80000000, SZ_512M, fdt);
}
/**
* @brief The basic entry point for board initialization.
*
* This is called as part of machine init (after arch init).
* This is again called with stack in SRAM, so not too many
* constructs possible here.
*
* @return void
*/
static noinline int gf_sram_init(void)
{
void *fdt;
fdt = __dtb_z_am335x_afi_gf_start;
/* WDT1 is already running when the bootloader gets control
* Disable it to avoid "random" resets
*/
__raw_writel(WDT_DISABLE_CODE1, AM33XX_WDT_REG(WSPR));
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
__raw_writel(WDT_DISABLE_CODE2, AM33XX_WDT_REG(WSPR));
while(__raw_readl(AM33XX_WDT_REG(WWPS)) != 0x0);
/* Setup the PLLs and the clocks for the peripherals */
am33xx_pll_init(MPUPLL_M_500, DDRPLL_M_200);
board_config_ddr();
/*
* FIXME configure CAN pinmux early to avoid driving the bus
* with the low by default pins.
*/
configure_module_pin_mux(board_can_pin_mux);
am33xx_uart_soft_reset((void *)AM33XX_UART2_BASE);
am33xx_enable_uart2_pin_mux();
omap_uart_lowlevel_init((void *)AM33XX_UART2_BASE);
putc_ll('>');
barebox_arm_entry(0x80000000, SZ_256M, fdt);
}
