void ar7100_ddr_tap_set(uint8_t set) { ar7100_reg_wr_nf(AR7100_DDR_TAP_CONTROL0, set); ar7100_reg_wr_nf(AR7100_DDR_TAP_CONTROL1, set); ar7100_reg_wr_nf(AR7100_DDR_TAP_CONTROL2, set); ar7100_reg_wr_nf(AR7100_DDR_TAP_CONTROL3, set); }
static void ar7100_spi_write_enable() { ar7100_reg_wr_nf(AR7100_SPI_FS, 1); ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CS_DIS); ar7100_spi_bit_banger(AR7100_SPI_CMD_WREN); ar7100_spi_go(); }
static void ar7100_spi_bit_banger(unsigned char _byte) { int i; for (i = 0; i < 8; i++) { ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CE_LOW | ar7100_be_msb(_byte, i)); ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CE_HIGH | ar7100_be_msb(_byte, i)); } }
int generic_spi_access_done(void) { generic_i2c_deassert_cs(); ar7100_reg_wr_nf(GENERIC_SPI_FS, 0); unprotect(); return 0; }
static void ar7100_spi_poll() { int rd; do { ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CS_DIS); ar7100_spi_bit_banger(AR7100_SPI_CMD_RD_STATUS); ar7100_spi_delay_8(); rd = (ar7100_reg_rd(AR7100_SPI_RD_STATUS) & 1); }while(rd); }
static void read_id() { u32 rd = 0x777777; ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CS_DIS); ar7100_spi_bit_banger(0x9f); ar7100_spi_delay_8(); ar7100_spi_delay_8(); ar7100_spi_delay_8(); ar7100_spi_done(); /* rd = ar7100_reg_rd(AR7100_SPI_RD_STATUS); */ rd = ar7100_reg_rd(AR7100_SPI_READ); printf("id read %#x\n", rd); }
int generic_spi_access_enable(int cs) { protect(); ar7100_reg_wr(GENERIC_SPI_CLOCK, 0x43); /* Enable access to SPI bits through memory * mapped registers. */ ar7100_reg_wr_nf(GENERIC_SPI_FS, 1); ar7100_reg_wr_nf(GENERIC_SPI_WRITE, GENERIC_SPI_CS_DIS); { unsigned int cs0to2mask; cs0to2mask = ar7100_reg_rd(GENERIC_SPI_WRITE) & GENERIC_SPI_CS_DIS; ar7100_reg_wr (GENERIC_SPI_WRITE, cs0to2mask | GENERIC_SPI_CLK_HIGH ); } generic_i2c_assert_cs(cs); return 0; }
unsigned long flash_init (void) { int i; u32 rd = 0x666666; ar7100_reg_wr_nf(AR7100_SPI_CLOCK, 0x43); ar7100_spi_flash_unblock(); read_id(); /* rd = ar7100_reg_rd(AR7100_SPI_RD_STATUS); printf ("rd = %x\n", rd); if (rd & 0x80) { } */ /* * hook into board specific code to fill flash_info */ return (flash_get_geom(&flash_info)); }
void ar7100_ddr_initial_config(uint32_t refresh) { printf("\nsri :ddr_init\n"); ar7100_reg_wr_nf(AR7100_DDR_CONFIG, CFG_DDR_CONFIG_VAL); udelay(1000); ar7100_reg_wr_nf(AR7100_DDR_CONFIG2, CFG_DDR_CONFIG2_VAL); udelay(1000); ar7100_reg_wr_nf(AR7100_DDR_CONTROL, 0x8); udelay(1000); #ifdef AR9100 ar7100_reg_wr_nf(AR7100_DDR_MODE, CFG_DDR_MODE_VAL_INIT); udelay(1000); #endif ar7100_reg_wr_nf(AR7100_DDR_CONTROL, 0x1); udelay(1000); ar7100_reg_wr_nf(AR7100_DDR_EXT_MODE, CFG_DDR_EXT_MODE_VAL); udelay(1000); ar7100_reg_wr_nf(AR7100_DDR_CONTROL, 0x2); udelay(1000); ar7100_reg_wr_nf(AR7100_DDR_CONTROL, 0x8); udelay(1000); ar7100_reg_wr_nf(AR7100_DDR_MODE, CFG_DDR_MODE_VAL); udelay(10000); ar7100_reg_wr_nf(AR7100_DDR_CONTROL, 0x1); udelay(1000); ar7100_reg_wr_nf(AR7100_DDR_REFRESH, refresh); udelay(1000); ar7100_reg_wr_nf(AR7100_DDR_RD_DATA_THIS_CYCLE, CFG_DDR_RD_DATA_THIS_CYCLE_VAL); udelay(1000); printf("done\n"); }
static void ar7100_spi_go(void) { ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CE_LOW); ar7100_reg_wr_nf(AR7100_SPI_WRITE, AR7100_SPI_CS_DIS); }