static void __init ar71xx_pci_irq_init(void)
{
int i;
ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE, 0);
ar71xx_reset_wr(RESET_REG_PCI_INT_STATUS, 0);
for (i = AR71XX_PCI_IRQ_BASE;
i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
irq_desc[i].status = IRQ_DISABLED;
set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
handle_level_irq);
}
setup_irq(AR71XX_CPU_IRQ_PCI, &ar71xx_pci_irqaction);
}
void ar71xx_device_start(u32 mask)
{
unsigned long flags;
u32 mask_inv;
u32 t;
switch (ar71xx_soc) {
case AR71XX_SOC_AR7130:
case AR71XX_SOC_AR7141:
case AR71XX_SOC_AR7161:
local_irq_save(flags);
t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE);
ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask);
local_irq_restore(flags);
break;
case AR71XX_SOC_AR7240:
mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240;
local_irq_save(flags);
t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
t &= ~mask;
t |= mask_inv;
ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t);
local_irq_restore(flags);
break;
case AR71XX_SOC_AR9130:
case AR71XX_SOC_AR9132:
local_irq_save(flags);
t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE);
ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask);
local_irq_restore(flags);
break;
default:
BUG();
}
}
static void ar71xx_pci_irq_mask(unsigned int irq)
{
irq -= AR71XX_PCI_IRQ_BASE;
ar71xx_reset_wr(RESET_REG_PCI_INT_ENABLE,
ar71xx_reset_rr(RESET_REG_PCI_INT_ENABLE) & ~(1 << irq));
}
static void ar71xx_misc_irq_unmask(unsigned int irq)
{
irq -= AR71XX_MISC_IRQ_BASE;
ar71xx_reset_wr(RESET_REG_MISC_INT_ENABLE,
ar71xx_reset_rr(RESET_REG_MISC_INT_ENABLE) | (1 << irq));
}
static inline void ar71xx_wdt_disable(void)
{
printk(KERN_DEBUG DRV_NAME ": disabling watchdog timer\n");
ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE);
}
static inline void ar71xx_wdt_enable(void)
{
printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n");
ar71xx_wdt_keepalive();
ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR);
}
static inline void ar71xx_wdt_keepalive(void)
{
ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, ar71xx_ahb_freq * wdt_timeout);
}