int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp) { arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t)); arm9tdmi_init_arch_info(target, arm9tdmi, target->tap); return ERROR_OK; }
static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp) { struct arm7_9_common *arm7_9 = calloc(1, sizeof(struct arm7_9_common)); arm9tdmi_init_arch_info(target, arm7_9, target->tap); arm7_9->arm.is_armv4 = true; return ERROR_OK; }
int arm966e_init_arch_info(struct target *target, struct arm966e_common *arm966e, struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm966e->arm7_9_common; /* initialize arm7/arm9 specific info (including armv4_5) */ arm9tdmi_init_arch_info(target, arm7_9, tap); arm966e->common_magic = ARM966E_COMMON_MAGIC; /* The ARM966E-S implements the ARMv5TE architecture which * has the BKPT instruction, so we don't have to use a watchpoint comparator */ arm7_9->arm_bkpt = ARMV5_BKPT(0x0); arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; return ERROR_OK; }
/* target arm9tdmi <endianess> <startup_mode> <chain_pos> <variant>*/ int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target) { int chain_pos; char *variant = NULL; arm9tdmi_common_t *arm9tdmi = malloc(sizeof(arm9tdmi_common_t)); if (argc < 4) { ERROR("'target arm9tdmi' requires at least one additional argument"); exit(-1); } chain_pos = strtoul(args[3], NULL, 0); if (argc >= 5) variant = args[4]; arm9tdmi_init_arch_info(target, arm9tdmi, chain_pos, variant); return ERROR_OK; }
int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm926ejs, struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm926ejs->arm7_9_common; arm7_9->arm.mrc = arm926ejs_mrc; arm7_9->arm.mcr = arm926ejs_mcr; /* initialize arm7/arm9 specific info (including armv4_5) */ arm9tdmi_init_arch_info(target, arm7_9, tap); arm926ejs->common_magic = ARM926EJS_COMMON_MAGIC; arm7_9->post_debug_entry = arm926ejs_post_debug_entry; arm7_9->pre_restore_context = arm926ejs_pre_restore_context; arm7_9->write_memory = arm926ejs_write_memory; arm926ejs->read_cp15 = arm926ejs_cp15_read; arm926ejs->write_cp15 = arm926ejs_cp15_write; arm926ejs->armv4_5_mmu.armv4_5_cache.ctype = -1; arm926ejs->armv4_5_mmu.get_ttb = arm926ejs_get_ttb; arm926ejs->armv4_5_mmu.read_memory = arm7_9_read_memory; arm926ejs->armv4_5_mmu.write_memory = arm7_9_write_memory; arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches; arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches; arm926ejs->armv4_5_mmu.has_tiny_pages = 1; arm926ejs->armv4_5_mmu.mmu_enabled = 0; arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason; /* The ARM926EJ-S implements the ARMv5TE architecture which * has the BKPT instruction, so we don't have to use a watchpoint comparator */ arm7_9->arm_bkpt = ARMV5_BKPT(0x0); arm7_9->thumb_bkpt = ARMV5_T_BKPT(0x0) & 0xffff; return ERROR_OK; }
static int arm920t_init_arch_info(struct target *target, struct arm920t_common *arm920t, struct jtag_tap *tap) { struct arm7_9_common *arm7_9 = &arm920t->arm7_9_common; arm7_9->arm.mrc = arm920t_mrc; arm7_9->arm.mcr = arm920t_mcr; /* initialize arm7/arm9 specific info (including armv4_5) */ arm9tdmi_init_arch_info(target, arm7_9, tap); arm920t->common_magic = ARM920T_COMMON_MAGIC; arm7_9->post_debug_entry = arm920t_post_debug_entry; arm7_9->pre_restore_context = arm920t_pre_restore_context; arm7_9->write_memory = arm920t_write_memory; arm920t->armv4_5_mmu.armv4_5_cache.ctype = -1; arm920t->armv4_5_mmu.get_ttb = arm920t_get_ttb; arm920t->armv4_5_mmu.read_memory = arm7_9_read_memory; arm920t->armv4_5_mmu.write_memory = arm7_9_write_memory; arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches; arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches; arm920t->armv4_5_mmu.has_tiny_pages = 1; arm920t->armv4_5_mmu.mmu_enabled = 0; /* disabling linefills leads to lockups, so keep them enabled for now * this doesn't affect correctness, but might affect timing issues, if * important data is evicted from the cache during the debug session * */ arm920t->preserve_cache = 0; /* override hw single-step capability from ARM9TDMI */ arm7_9->has_single_step = 1; return ERROR_OK; }