/*
* Access PHYs integrated into the switch chip through the switch's MDIO
* control register.
*/
int
arswitch_readphy_internal(device_t dev, int phy, int reg)
{
struct arswitch_softc *sc;
uint32_t data = 0, ctrl;
int err, timeout;
uint32_t a;
sc = device_get_softc(dev);
ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
if (phy < 0 || phy >= 32)
return (ENXIO);
if (reg < 0 || reg >= 32)
return (ENXIO);
if (AR8X16_IS_SWITCH(sc, AR8327))
a = AR8327_REG_MDIO_CTRL;
else
a = AR8X16_REG_MDIO_CTRL;
ARSWITCH_LOCK(sc);
err = arswitch_writereg_msb(dev, a,
AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN |
AR8X16_MDIO_CTRL_CMD_READ |
(phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
(reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);
if (err != 0)
goto fail;
for (timeout = 100; timeout--; ) {
ctrl = arswitch_readreg_msb(dev, a);
if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
break;
}
if (timeout < 0) {
DPRINTF(sc, ARSWITCH_DBG_ANY,
"arswitch_readphy(): phy=%d.%02x; timeout=%d\n",
phy, reg, timeout);
goto fail;
}
data = arswitch_readreg_lsb(dev, a) &
AR8X16_MDIO_CTRL_DATA_MASK;
ARSWITCH_UNLOCK(sc);
DPRINTF(sc, ARSWITCH_DBG_PHYIO,
"%s: phy=0x%08x, reg=0x%08x, ret=0x%08x\n",
__func__, phy, reg, data);
return (data);
fail:
ARSWITCH_UNLOCK(sc);
DPRINTF(sc, ARSWITCH_DBG_PHYIO,
"%s: phy=0x%08x, reg=0x%08x, fail; err=%d\n",
__func__, phy, reg, err);
return (-1);
}
/*
* access PHYs integrated into the switch chip through the switch's MDIO
* control register.
*/
int
arswitch_readphy(device_t dev, int phy, int reg)
{
uint32_t data = 0, ctrl;
int err, timeout;
if (phy < 0 || phy >= 32)
return (ENXIO);
if (reg < 0 || reg >= 32)
return (ENXIO);
err = arswitch_writereg_msb(dev, AR8X16_REG_MDIO_CTRL,
AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN |
AR8X16_MDIO_CTRL_CMD_READ |
(phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
(reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);
if (err != 0)
return (-1);
for (timeout = 100; timeout--; ) {
ctrl = arswitch_readreg_msb(dev, AR8X16_REG_MDIO_CTRL);
if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
break;
}
if (timeout < 0)
err = EIO;
data = arswitch_readreg_lsb(dev, AR8X16_REG_MDIO_CTRL) &
AR8X16_MDIO_CTRL_DATA_MASK;
return (data);
}
/*
* access PHYs integrated into the switch chip through the switch's MDIO
* control register.
*/
int
arswitch_readphy(device_t dev, int phy, int reg)
{
struct arswitch_softc *sc;
uint32_t data = 0, ctrl;
int err, timeout;
sc = device_get_softc(dev);
ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
if (phy < 0 || phy >= 32)
return (ENXIO);
if (reg < 0 || reg >= 32)
return (ENXIO);
ARSWITCH_LOCK(sc);
err = arswitch_writereg_msb(dev, AR8X16_REG_MDIO_CTRL,
AR8X16_MDIO_CTRL_BUSY | AR8X16_MDIO_CTRL_MASTER_EN |
AR8X16_MDIO_CTRL_CMD_READ |
(phy << AR8X16_MDIO_CTRL_PHY_ADDR_SHIFT) |
(reg << AR8X16_MDIO_CTRL_REG_ADDR_SHIFT));
DEVERR(dev, err, "arswitch_readphy()=%d: phy=%d.%02x\n", phy, reg);
if (err != 0)
goto fail;
for (timeout = 100; timeout--; ) {
ctrl = arswitch_readreg_msb(dev, AR8X16_REG_MDIO_CTRL);
if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
break;
}
if (timeout < 0)
goto fail;
data = arswitch_readreg_lsb(dev, AR8X16_REG_MDIO_CTRL) &
AR8X16_MDIO_CTRL_DATA_MASK;
ARSWITCH_UNLOCK(sc);
return (data);
fail:
ARSWITCH_UNLOCK(sc);
return (-1);
}
