static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
{
struct at91_cf_socket *cf;
u32 csr;
cf = container_of(s, struct at91_cf_socket, socket);
io->flags &= (MAP_ACTIVE | MAP_16BIT | MAP_AUTOSZ);
/*
*/
csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
/*
*/
if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) {
csr |= AT91_SMC_DBW_8;
pr_debug("%s: 8bit i/o bus\n", driver_name);
} else {
csr |= AT91_SMC_DBW_16;
pr_debug("%s: 16bit i/o bus\n", driver_name);
}
at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr);
io->start = cf->socket.io_offset;
io->stop = io->start + SZ_2K - 1;
return 0;
}
void __init at91_add_device_nand(struct atmel_nand_data *data)
{
unsigned int csa;
if (!data)
return;
/* enable the address range of CS3 */
csa = at91_ramc_read(0, AT91_EBI_CSA);
at91_ramc_write(0, AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
/* set the bus interface characteristics */
at91_ramc_write(0, AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
| AT91_SMC_NWS_(5)
| AT91_SMC_TDF_(1)
| AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
| AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
at91_set_gpio_output(data->enable_pin, 1);
/* ready/busy pin */
if (gpio_is_valid(data->rdy_pin))
at91_set_gpio_input(data->rdy_pin, 1);
/* card detect pin */
if (gpio_is_valid(data->det_pin))
at91_set_gpio_input(data->det_pin, 1);
at91_set_A_periph(AT91_PIN_PC1, 0); /* SMOE */
at91_set_A_periph(AT91_PIN_PC3, 0); /* SMWE */
nand_data = *data;
platform_device_register(&at91rm9200_nand_device);
}
/* we already mapped the I/O region */
static int at91_cf_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
{
struct at91_cf_socket *cf;
u32 csr;
cf = container_of(s, struct at91_cf_socket, socket);
io->flags &= (MAP_ACTIVE | MAP_16BIT | MAP_AUTOSZ);
/*
* Use 16 bit accesses unless/until we need 8-bit i/o space.
*/
csr = at91_ramc_read(0, AT91_SMC_CSR(cf->board->chipselect)) & ~AT91_SMC_DBW;
/*
* NOTE: this CF controller ignores IOIS16, so we can't really do
* MAP_AUTOSZ. The 16bit mode allows single byte access on either
* D0-D7 (even addr) or D8-D15 (odd), so it's close enough for many
* purposes (and handles ide-cs).
*
* The 8bit mode is needed for odd byte access on D0-D7. It seems
* some cards only like that way to get at the odd byte, despite
* CF 3.0 spec table 35 also giving the D8-D15 option.
*/
if (!(io->flags & (MAP_16BIT | MAP_AUTOSZ))) {
csr |= AT91_SMC_DBW_8;
dev_dbg(&cf->pdev->dev, "8bit i/o bus\n");
} else {
csr |= AT91_SMC_DBW_16;
dev_dbg(&cf->pdev->dev, "16bit i/o bus\n");
}
at91_ramc_write(0, AT91_SMC_CSR(cf->board->chipselect), csr);
io->start = cf->socket.io_offset;
io->stop = io->start + SZ_2K - 1;
return 0;
}
