/* The stock firmware does not support setting the coverage class. Instead this
* function monitors and modifies the corresponding MAC registers.
*/
static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
s16 value)
{
u32 slottime_reg;
u32 slottime;
u32 timeout_reg;
u32 ack_timeout;
u32 cts_timeout;
u32 phyclk_reg;
u32 phyclk;
u64 fw_dbglog_mask;
u32 fw_dbglog_level;
mutex_lock(&ar->conf_mutex);
/* Only modify registers if the core is started. */
if ((ar->state != ATH10K_STATE_ON) &&
(ar->state != ATH10K_STATE_RESTARTED)) {
spin_lock_bh(&ar->data_lock);
/* Store config value for when radio boots up */
ar->fw_coverage.coverage_class = value;
spin_unlock_bh(&ar->data_lock);
goto unlock;
}
/* Retrieve the current values of the two registers that need to be
* adjusted.
*/
slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
WAVE1_PCU_GBL_IFS_SLOT);
timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
WAVE1_PCU_ACK_CTS_TIMEOUT);
phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
WAVE1_PHYCLK);
phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;
if (value < 0)
value = ar->fw_coverage.coverage_class;
/* Break out if the coverage class and registers have the expected
* value.
*/
if (value == ar->fw_coverage.coverage_class &&
slottime_reg == ar->fw_coverage.reg_slottime_conf &&
timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
phyclk_reg == ar->fw_coverage.reg_phyclk)
goto unlock;
{
static int did_once = 0;
if (!did_once) {
ath10k_warn(ar, "set-coverage-class, phyclk: %d value: %d\n", phyclk, value);
did_once = true;
}
}
/* Store new initial register values from the firmware. */
if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
ar->fw_coverage.reg_slottime_orig = slottime_reg;
if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
ar->fw_coverage.reg_phyclk = phyclk_reg;
/* Calculate new value based on the (original) firmware calculation. */
slottime_reg = ar->fw_coverage.reg_slottime_orig;
timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;
/* Do some sanity checks on the slottime register. */
if (slottime_reg % phyclk) {
ath10k_warn(ar,
"failed to set coverage class: expected integer microsecond value in register\n");
goto store_regs;
}
slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
slottime = slottime / phyclk;
if (slottime != 9 && slottime != 20) {
ath10k_warn(ar,
"failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",
slottime);
goto store_regs;
}
/* Recalculate the register values by adding the additional propagation
* delay (3us per coverage class).
*/
slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
slottime += value * 3 * phyclk;
slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX);
slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT);
slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime;
/* Update ack timeout (lower halfword). */
ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
ack_timeout += 3 * value * phyclk;
ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
/* Update cts timeout (upper halfword). */
cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
cts_timeout += 3 * value * phyclk;
cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
timeout_reg = ack_timeout | cts_timeout;
ath10k_hif_write32(ar,
WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT,
slottime_reg);
ath10k_hif_write32(ar,
WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT,
timeout_reg);
if (test_bit(ATH10K_FW_FEATURE_SET_SPECIAL_CT,
ar->running_fw->fw_file.fw_features)) {
/* CT firmware can set and make this value stick w/out all the hackery,
* but go ahead and use this logic to calculate the appropriate values.
* We should then short-circuit this logic earlier in this method because
* the values in the firmware will already match expected values.
* --Ben
*/
ar->eeprom_overrides.reg_ack_cts = timeout_reg;
ar->eeprom_overrides.reg_ifs_slot = slottime_reg;
ath10k_wmi_pdev_set_special(ar, SET_SPECIAL_ID_ACK_CTS, ar->eeprom_overrides.reg_ack_cts);
ath10k_wmi_pdev_set_special(ar, SET_SPECIAL_ID_SLOT, ar->eeprom_overrides.reg_ifs_slot);
ar->eeprom_overrides.coverage_already_set = true;
}
/* Ensure we have a debug level of WARN set for the case that the
* coverage class is larger than 0. This is important as we need to
* set the registers again if the firmware does an internal reset and
* this way we will be notified of the event.
*/
fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);
fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);
if (value > 0) {
if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN)
fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN;
fw_dbglog_mask = ~0;
}
ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);
store_regs:
/* After an error we will not retry setting the coverage class. */
spin_lock_bh(&ar->data_lock);
ar->fw_coverage.coverage_class = value;
spin_unlock_bh(&ar->data_lock);
ar->fw_coverage.reg_slottime_conf = slottime_reg;
ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;
unlock:
mutex_unlock(&ar->conf_mutex);
}
/* The firmware does not support setting the coverage class. Instead this
* function monitors and modifies the corresponding MAC registers.
*/
static void ath10k_hw_qca988x_set_coverage_class(struct ath10k *ar,
s16 value)
{
u32 slottime_reg;
u32 slottime;
u32 timeout_reg;
u32 ack_timeout;
u32 cts_timeout;
u32 phyclk_reg;
u32 phyclk;
u64 fw_dbglog_mask;
u32 fw_dbglog_level;
mutex_lock(&ar->conf_mutex);
/* Only modify registers if the core is started. */
if ((ar->state != ATH10K_STATE_ON) &&
(ar->state != ATH10K_STATE_RESTARTED))
goto unlock;
/* Retrieve the current values of the two registers that need to be
* adjusted.
*/
slottime_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
WAVE1_PCU_GBL_IFS_SLOT);
timeout_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
WAVE1_PCU_ACK_CTS_TIMEOUT);
phyclk_reg = ath10k_hif_read32(ar, WLAN_MAC_BASE_ADDRESS +
WAVE1_PHYCLK);
phyclk = MS(phyclk_reg, WAVE1_PHYCLK_USEC) + 1;
if (value < 0)
value = ar->fw_coverage.coverage_class;
/* Break out if the coverage class and registers have the expected
* value.
*/
if (value == ar->fw_coverage.coverage_class &&
slottime_reg == ar->fw_coverage.reg_slottime_conf &&
timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf &&
phyclk_reg == ar->fw_coverage.reg_phyclk)
goto unlock;
/* Store new initial register values from the firmware. */
if (slottime_reg != ar->fw_coverage.reg_slottime_conf)
ar->fw_coverage.reg_slottime_orig = slottime_reg;
if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf)
ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg;
ar->fw_coverage.reg_phyclk = phyclk_reg;
/* Calculat new value based on the (original) firmware calculation. */
slottime_reg = ar->fw_coverage.reg_slottime_orig;
timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig;
/* Do some sanity checks on the slottime register. */
if (slottime_reg % phyclk) {
ath10k_warn(ar,
"failed to set coverage class: expected integer microsecond value in register\n");
goto store_regs;
}
slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
slottime = slottime / phyclk;
if (slottime != 9 && slottime != 20) {
ath10k_warn(ar,
"failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n",
slottime);
goto store_regs;
}
/* Recalculate the register values by adding the additional propagation
* delay (3us per coverage class).
*/
slottime = MS(slottime_reg, WAVE1_PCU_GBL_IFS_SLOT);
slottime += value * 3 * phyclk;
slottime = min_t(u32, slottime, WAVE1_PCU_GBL_IFS_SLOT_MAX);
slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT);
slottime_reg = (slottime_reg & ~WAVE1_PCU_GBL_IFS_SLOT_MASK) | slottime;
/* Update ack timeout (lower halfword). */
ack_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
ack_timeout += 3 * value * phyclk;
ack_timeout = min_t(u32, ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK);
/* Update cts timeout (upper halfword). */
cts_timeout = MS(timeout_reg, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
cts_timeout += 3 * value * phyclk;
cts_timeout = min_t(u32, cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_MAX);
cts_timeout = SM(cts_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_CTS);
timeout_reg = ack_timeout | cts_timeout;
ath10k_hif_write32(ar,
WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_GBL_IFS_SLOT,
slottime_reg);
ath10k_hif_write32(ar,
WLAN_MAC_BASE_ADDRESS + WAVE1_PCU_ACK_CTS_TIMEOUT,
timeout_reg);
/* Ensure we have a debug level of WARN set for the case that the
* coverage class is larger than 0. This is important as we need to
* set the registers again if the firmware does an internal reset and
* this way we will be notified of the event.
*/
fw_dbglog_mask = ath10k_debug_get_fw_dbglog_mask(ar);
fw_dbglog_level = ath10k_debug_get_fw_dbglog_level(ar);
if (value > 0) {
if (fw_dbglog_level > ATH10K_DBGLOG_LEVEL_WARN)
fw_dbglog_level = ATH10K_DBGLOG_LEVEL_WARN;
fw_dbglog_mask = ~0;
}
ath10k_wmi_dbglog_cfg(ar, fw_dbglog_mask, fw_dbglog_level);
store_regs:
/* After an error we will not retry setting the coverage class. */
spin_lock_bh(&ar->data_lock);
ar->fw_coverage.coverage_class = value;
spin_unlock_bh(&ar->data_lock);
ar->fw_coverage.reg_slottime_conf = slottime_reg;
ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg;
unlock:
mutex_unlock(&ar->conf_mutex);
}
/* Program CPU_ADDR_MSB to allow different memory
* region access.
*/
static void ath10k_hw_map_target_mem(struct ath10k *ar, u32 msb)
{
u32 address = SOC_CORE_BASE_ADDRESS + FW_RAM_CONFIG_ADDRESS;
ath10k_hif_write32(ar, address, msb);
}