/*
* Set HTC/Mbox operational parameters, this can only be called when the
* target is in the BMI phase.
*/
static int ath6kl_set_htc_params(struct ath6kl *ar, u32 mbox_isr_yield_val,
u8 htc_ctrl_buf)
{
int status;
u32 blk_size;
blk_size = ar->mbox_info.block_size;
if (htc_ctrl_buf)
blk_size |= ((u32)htc_ctrl_buf) << 16;
/* set the host interest area for the block size */
status = ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_mbox_io_block_sz)),
(u8 *)&blk_size,
4);
if (status) {
ath6kl_err("bmi_write_memory for IO block size failed\n");
goto out;
}
ath6kl_dbg(ATH6KL_DBG_TRC, "block size set: %d (target addr:0x%X)\n",
blk_size,
ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_mbox_io_block_sz)));
if (mbox_isr_yield_val) {
/* set the host interest area for the mbox ISR yield limit */
status = ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_mbox_isr_yield_limit)),
(u8 *)&mbox_isr_yield_val,
4);
if (status) {
ath6kl_err("bmi_write_memory for yield limit failed\n");
goto out;
}
}
out:
return status;
}
static void ath6kl_hif_dump_fw_crash(struct ath6kl *ar)
{
__le32 regdump_val[REGISTER_DUMP_LEN_MAX];
u32 i, address, regdump_addr = 0;
int ret;
if (ar->target_type != TARGET_TYPE_AR6003)
return;
/* the reg dump pointer is copied to the host interest area */
address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state));
address = TARG_VTOP(ar->target_type, address);
/* read RAM location through diagnostic window */
ret = ath6kl_diag_read32(ar, address, ®dump_addr);
if (ret || !regdump_addr) {
ath6kl_warn("failed to get ptr to register dump area: %d\n",
ret);
return;
}
ath6kl_dbg(ATH6KL_DBG_IRQ, "register dump data address 0x%x\n",
regdump_addr);
regdump_addr = TARG_VTOP(ar->target_type, regdump_addr);
/* fetch register dump data */
ret = ath6kl_diag_read(ar, regdump_addr, (u8 *)®dump_val[0],
REG_DUMP_COUNT_AR6003 * (sizeof(u32)));
if (ret) {
ath6kl_warn("failed to get register dump: %d\n", ret);
return;
}
ath6kl_info("crash dump:\n");
ath6kl_info("hw 0x%x fw %s\n", ar->wiphy->hw_version,
ar->wiphy->fw_version);
BUILD_BUG_ON(REG_DUMP_COUNT_AR6003 % 4);
for (i = 0; i < REG_DUMP_COUNT_AR6003 / 4; i++) {
ath6kl_info("%d: 0x%8.8x 0x%8.8x 0x%8.8x 0x%8.8x\n",
4 * i,
le32_to_cpu(regdump_val[i]),
le32_to_cpu(regdump_val[i + 1]),
le32_to_cpu(regdump_val[i + 2]),
le32_to_cpu(regdump_val[i + 3]));
}
}
static void ath6kl_dump_target_assert_info(struct ath6kl *ar)
{
u32 address;
u32 regdump_loc = 0;
int status;
u32 regdump_val[REGISTER_DUMP_LEN_MAX];
u32 i;
if (ar->target_type != TARGET_TYPE_AR6003)
return;
/* the reg dump pointer is copied to the host interest area */
address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_failure_state));
address = TARG_VTOP(address);
/* read RAM location through diagnostic window */
status = ath6kl_read_reg_diag(ar, &address, ®dump_loc);
if (status || !regdump_loc) {
ath6kl_err("failed to get ptr to register dump area\n");
return;
}
ath6kl_dbg(ATH6KL_DBG_TRC, "location of register dump data: 0x%X\n",
regdump_loc);
regdump_loc = TARG_VTOP(regdump_loc);
/* fetch register dump data */
status = ath6kl_access_datadiag(ar,
regdump_loc,
(u8 *)®dump_val[0],
REG_DUMP_COUNT_AR6003 * (sizeof(u32)),
true);
if (status) {
ath6kl_err("failed to get register dump\n");
return;
}
ath6kl_dbg(ATH6KL_DBG_TRC, "Register Dump:\n");
for (i = 0; i < REG_DUMP_COUNT_AR6003; i++)
ath6kl_dbg(ATH6KL_DBG_TRC, " %d : 0x%8.8X\n",
i, regdump_val[i]);
}
static int ath6kl_upload_patch(struct ath6kl *ar)
{
const char *filename;
u32 address, param;
int ret;
switch (ar->version.target_ver) {
case AR6003_REV2_VERSION:
filename = AR6003_REV2_PATCH_FILE;
break;
default:
filename = AR6003_REV3_PATCH_FILE;
break;
}
if (ar->fw_patch == NULL) {
ret = ath6kl_get_fw(ar, filename, &ar->fw_patch,
&ar->fw_patch_len);
if (ret) {
ath6kl_err("Failed to get patch file %s: %d\n",
filename, ret);
return ret;
}
}
address = ath6kl_get_load_address(ar->version.target_ver,
DATASET_PATCH_ADDR);
ret = ath6kl_bmi_write(ar, address, ar->fw_patch, ar->fw_patch_len);
if (ret) {
ath6kl_err("Failed to write patch file: %d\n", ret);
return ret;
}
param = address;
ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_dset_list_head)),
(unsigned char *) ¶m, 4);
return 0;
}
static int ath6kl_set_host_app_area(struct ath6kl *ar)
{
u32 address, data;
struct host_app_area host_app_area;
/* Fetch the address of the host_app_area_s
* instance in the host interest area */
address = ath6kl_get_hi_item_addr(ar, HI_ITEM(hi_app_host_interest));
address = TARG_VTOP(address);
if (ath6kl_read_reg_diag(ar, &address, &data))
return -EIO;
address = TARG_VTOP(data);
host_app_area.wmi_protocol_ver = WMI_PROTOCOL_VERSION;
if (ath6kl_access_datadiag(ar, address,
(u8 *)&host_app_area,
sizeof(struct host_app_area), false))
return -EIO;
return 0;
}
static int ath6kl_init_upload(struct ath6kl *ar)
{
u32 param, options, sleep, address;
int status = 0;
if (ar->target_type != TARGET_TYPE_AR6003)
return -EINVAL;
/* temporarily disable system sleep */
address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
status = ath6kl_bmi_reg_read(ar, address, ¶m);
if (status)
return status;
options = param;
param |= ATH6KL_OPTION_SLEEP_DISABLE;
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
status = ath6kl_bmi_reg_read(ar, address, ¶m);
if (status)
return status;
sleep = param;
param |= SM(SYSTEM_SLEEP_DISABLE, 1);
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
ath6kl_dbg(ATH6KL_DBG_TRC, "old options: %d, old sleep: %d\n",
options, sleep);
/* program analog PLL register */
status = ath6kl_bmi_reg_write(ar, ATH6KL_ANALOG_PLL_REGISTER,
0xF9104001);
if (status)
return status;
/* Run at 80/88MHz by default */
param = SM(CPU_CLOCK_STANDARD, 1);
address = RTC_BASE_ADDRESS + CPU_CLOCK_ADDRESS;
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
param = 0;
address = RTC_BASE_ADDRESS + LPO_CAL_ADDRESS;
param = SM(LPO_CAL_ENABLE, 1);
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
/* WAR to avoid SDIO CRC err */
if (ar->version.target_ver == AR6003_REV2_VERSION) {
ath6kl_err("temporary war to avoid sdio crc error\n");
param = 0x20;
address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
address = GPIO_BASE_ADDRESS + GPIO_PIN11_ADDRESS;
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
address = GPIO_BASE_ADDRESS + GPIO_PIN12_ADDRESS;
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
address = GPIO_BASE_ADDRESS + GPIO_PIN13_ADDRESS;
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
}
/* write EEPROM data to Target RAM */
status = ath6kl_upload_board_file(ar);
if (status)
return status;
/* transfer One time Programmable data */
status = ath6kl_upload_otp(ar);
if (status)
return status;
/* Download Target firmware */
status = ath6kl_upload_firmware(ar);
if (status)
return status;
status = ath6kl_upload_patch(ar);
if (status)
return status;
/* Restore system sleep */
address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
status = ath6kl_bmi_reg_write(ar, address, sleep);
if (status)
return status;
address = MBOX_BASE_ADDRESS + LOCAL_SCRATCH_ADDRESS;
param = options | 0x20;
status = ath6kl_bmi_reg_write(ar, address, param);
if (status)
return status;
/* Configure GPIO AR6003 UART */
param = CONFIG_AR600x_DEBUG_UART_TX_PIN;
status = ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_dbg_uart_txpin)),
(u8 *)¶m, 4);
return status;
}
static int ath6kl_upload_board_file(struct ath6kl *ar)
{
u32 board_address, board_ext_address, param;
int ret;
if (ar->fw_board == NULL) {
ret = ath6kl_fetch_board_file(ar);
if (ret)
return ret;
}
/* Determine where in Target RAM to write Board Data */
ath6kl_bmi_read(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_board_data)),
(u8 *) &board_address, 4);
ath6kl_dbg(ATH6KL_DBG_TRC, "board data download addr: 0x%x\n",
board_address);
/* determine where in target ram to write extended board data */
ath6kl_bmi_read(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_board_ext_data)),
(u8 *) &board_ext_address, 4);
ath6kl_dbg(ATH6KL_DBG_TRC, "board file download addr: 0x%x\n",
board_ext_address);
if (board_ext_address == 0) {
ath6kl_err("Failed to get board file target address.\n");
return -EINVAL;
}
if (ar->fw_board_len == (AR6003_BOARD_DATA_SZ +
AR6003_BOARD_EXT_DATA_SZ)) {
/* write extended board data */
ret = ath6kl_bmi_write(ar, board_ext_address,
ar->fw_board + AR6003_BOARD_DATA_SZ,
AR6003_BOARD_EXT_DATA_SZ);
if (ret) {
ath6kl_err("Failed to write extended board data: %d\n",
ret);
return ret;
}
/* record that extended board data is initialized */
param = (AR6003_BOARD_EXT_DATA_SZ << 16) | 1;
ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_board_ext_data_config)),
(unsigned char *) ¶m, 4);
}
if (ar->fw_board_len < AR6003_BOARD_DATA_SZ) {
ath6kl_err("Too small board file: %zu\n", ar->fw_board_len);
ret = -EINVAL;
return ret;
}
ret = ath6kl_bmi_write(ar, board_address, ar->fw_board,
AR6003_BOARD_DATA_SZ);
if (ret) {
ath6kl_err("Board file bmi write failed: %d\n", ret);
return ret;
}
/* record the fact that Board Data IS initialized */
param = 1;
ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_board_data_initialized)),
(u8 *)¶m, 4);
return ret;
}
int ath6kl_configure_target(struct ath6kl *ar)
{
u32 param, ram_reserved_size;
u8 fw_iftype;
fw_iftype = ath6kl_get_fw_iftype(ar);
if (fw_iftype == 0xff)
return -EINVAL;
/* Tell target which HTC version it is used*/
param = HTC_PROTOCOL_VERSION;
if (ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_app_host_interest)),
(u8 *)¶m, 4) != 0) {
ath6kl_err("bmi_write_memory for htc version failed\n");
return -EIO;
}
/* set the firmware mode to STA/IBSS/AP */
param = 0;
if (ath6kl_bmi_read(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_option_flag)),
(u8 *)¶m, 4) != 0) {
ath6kl_err("bmi_read_memory for setting fwmode failed\n");
return -EIO;
}
param |= (1 << HI_OPTION_NUM_DEV_SHIFT);
param |= (fw_iftype << HI_OPTION_FW_MODE_SHIFT);
param |= (0 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
param |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
if (ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_option_flag)),
(u8 *)¶m,
4) != 0) {
ath6kl_err("bmi_write_memory for setting fwmode failed\n");
return -EIO;
}
ath6kl_dbg(ATH6KL_DBG_TRC, "firmware mode set\n");
/*
* Hardcode the address use for the extended board data
* Ideally this should be pre-allocate by the OS at boot time
* But since it is a new feature and board data is loaded
* at init time, we have to workaround this from host.
* It is difficult to patch the firmware boot code,
* but possible in theory.
*/
if (ar->target_type == TARGET_TYPE_AR6003) {
if (ar->version.target_ver == AR6003_REV2_VERSION) {
param = AR6003_REV2_BOARD_EXT_DATA_ADDRESS;
ram_reserved_size = AR6003_REV2_RAM_RESERVE_SIZE;
} else {
param = AR6003_REV3_BOARD_EXT_DATA_ADDRESS;
ram_reserved_size = AR6003_REV3_RAM_RESERVE_SIZE;
}
if (ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_board_ext_data)),
(u8 *)¶m, 4) != 0) {
ath6kl_err("bmi_write_memory for hi_board_ext_data failed\n");
return -EIO;
}
if (ath6kl_bmi_write(ar,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_end_ram_reserve_sz)),
(u8 *)&ram_reserved_size, 4) != 0) {
ath6kl_err("bmi_write_memory for hi_end_ram_reserve_sz failed\n");
return -EIO;
}
}
/* set the block size for the target */
if (ath6kl_set_htc_params(ar, MBOX_YIELD_LIMIT, 0))
/* use default number of control buffers */
return -EIO;
return 0;
}
int ath6kl_read_fwlogs(struct ath6kl *ar)
{
struct ath6kl_dbglog_hdr debug_hdr;
struct ath6kl_dbglog_buf debug_buf;
u32 address, length, dropped, firstbuf, debug_hdr_addr;
int ret = 0, loop;
u8 *buf;
buf = kmalloc(ATH6KL_FWLOG_PAYLOAD_SIZE, GFP_KERNEL);
if (!buf)
return -ENOMEM;
address = TARG_VTOP(ar->target_type,
ath6kl_get_hi_item_addr(ar,
HI_ITEM(hi_dbglog_hdr)));
ret = ath6kl_diag_read32(ar, address, &debug_hdr_addr);
if (ret)
goto out;
/* Get the contents of the ring buffer */
if (debug_hdr_addr == 0) {
ath6kl_warn("Invalid address for debug_hdr_addr\n");
ret = -EINVAL;
goto out;
}
address = TARG_VTOP(ar->target_type, debug_hdr_addr);
ath6kl_diag_read(ar, address, &debug_hdr, sizeof(debug_hdr));
address = TARG_VTOP(ar->target_type,
le32_to_cpu(debug_hdr.dbuf_addr));
firstbuf = address;
dropped = le32_to_cpu(debug_hdr.dropped);
ath6kl_diag_read(ar, address, &debug_buf, sizeof(debug_buf));
loop = 100;
do {
address = TARG_VTOP(ar->target_type,
le32_to_cpu(debug_buf.buffer_addr));
length = le32_to_cpu(debug_buf.length);
if (length != 0 && (le32_to_cpu(debug_buf.length) <=
le32_to_cpu(debug_buf.bufsize))) {
length = ALIGN(length, 4);
ret = ath6kl_diag_read(ar, address,
buf, length);
if (ret)
goto out;
ath6kl_debug_fwlog_event(ar, buf, length);
}
address = TARG_VTOP(ar->target_type,
le32_to_cpu(debug_buf.next));
ath6kl_diag_read(ar, address, &debug_buf, sizeof(debug_buf));
if (ret)
goto out;
loop--;
if (WARN_ON(loop == 0)) {
ret = -ETIMEDOUT;
goto out;
}
} while (address != firstbuf);
out:
kfree(buf);
return ret;
}