static void __init om5p_acv2_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);
gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,
"PA DC/DC");
gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH");
/* temperature sensor */
platform_device_register(&om5pacv2_i2c_device);
i2c_register_board_info(0, om5pacv2_i2c_devs,
ARRAY_SIZE(om5pacv2_i2c_devs));
ath79_register_m25p80(&om5pacv2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),
om5pacv2_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om5pacv2_gpio_keys),
om5pacv2_gpio_keys);
ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);
om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
mdiobus_register_board_info(om5pacv2_an_mdio0_info,
ARRAY_SIZE(om5pacv2_an_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
/* GMAC0 is connected to the PHY4 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_pll_data.pll_1000 = 0x82000101;
ath79_eth0_pll_data.pll_100 = 0x80000101;
ath79_eth0_pll_data.pll_10 = 0x80001313;
ath79_register_eth(0);
/* GMAC1 is connected to MDIO1 in SGMII mode */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth1_data.phy_mask = BIT(1);
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init cus227_register_spi_devices(
struct spi_board_info const *info)
{
gpio_request(CUS227_GPIO_SPI_CLK, "SPI CLK");
ath79_gpio_output_select(CUS227_GPIO_SPI_CLK, AR934X_GPIO_OUT_MUX_SPI_CLK);
gpio_direction_output(CUS227_GPIO_SPI_CLK, 0);
gpio_request(CUS227_GPIO_SPI_MOSI, "SPI MOSI");
ath79_gpio_output_select(CUS227_GPIO_SPI_MOSI, AR934X_GPIO_OUT_MUX_SPI_MOSI);
gpio_direction_output(CUS227_GPIO_SPI_MOSI, 0);
gpio_request(CUS227_GPIO_SPI_CS1, "SPI CS1");
ath79_gpio_output_select(CUS227_GPIO_SPI_CS1, AR934X_GPIO_OUT_MUX_SPI_CS1);
gpio_direction_output(CUS227_GPIO_SPI_CS1, 0);
/* a dedicated GPIO pin is used as SPI MISO since SPI controller doesn't support modes other than mode-0 */
gpio_request(CUS227_GPIO_SPI_MISO, "SPI MISO");
ath79_gpio_input_select(CUS227_GPIO_SPI_MISO, AR934X_GPIO_IN_MUX_SPI_MISO);
gpio_direction_input(CUS227_GPIO_SPI_MISO);
ath79_spi_data.bus_num = 0;
ath79_spi_data.num_chipselect = 2;
ath79_spi_data.miso_line = CUS227_GPIO_SPI_MISO;
ath79_register_spi(&ath79_spi_data, info, 1);
}
static void __init dr344_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
ath79_register_m25p80(NULL);
ath79_gpio_direction_select(DR344_GPIO_LED_STATUS, true);
gpio_set_value(DR344_GPIO_LED_STATUS, 1);
ath79_gpio_output_select(DR344_GPIO_LED_STATUS, 0);
ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
gpio_set_value(DR344_GPIO_LED_LAN, 1);
ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
dr344_leds_gpio);
ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dr344_gpio_keys),
dr344_gpio_keys);
ath79_register_usb();
ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(dr344_mdio0_info,
ARRAY_SIZE(dr344_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
/* GMAC0 is connected to an AR8035 Gbps PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x02000000;
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_register_eth(1);
}
static void __init common_setup(bool dualband)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
ath79_register_m25p80(&wdr3500_flash_data);
if (dualband)
{
tplink_register_builtin_wmac1(WDR3500_WMAC_CALDATA_OFFSET, mac, -1);
}
ap9x_pci_setup_wmac_led_pin(0, 0);
tplink_register_ap91_wmac2(WDR3500_PCIE_CALDATA_OFFSET, mac, 2);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
if (dualband)
{
gpio_request_one(WDR3500_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
}
ath79_register_usb();
ath79_gpio_output_select(WDR3500_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK3);
ath79_gpio_output_select(WDR3500_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(WDR3500_GPIO_LED_LAN3,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(WDR3500_GPIO_LED_LAN4,
AR934X_GPIO_OUT_LED_LINK0);
ath79_gpio_output_select(WDR3500_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
}
static void __init om5p_an_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* temperature sensor */
platform_device_register(&om5pan_i2c_device);
i2c_register_board_info(0, om5pan_i2c_devs,
ARRAY_SIZE(om5pan_i2c_devs));
/* make lan / wan leds software controllable */
ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(&om5p_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio),
om5p_leds_gpio);
ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
ath79_setup_ar934x_eth_rx_delay(2, 2);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
mdiobus_register_board_info(om5p_an_mdio0_info,
ARRAY_SIZE(om5p_an_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
/* GMAC0 is connected to the PHY7 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_mask = BIT(7);
ath79_eth0_pll_data.pll_1000 = 0x02000000;
ath79_eth0_pll_data.pll_100 = 0x00000101;
ath79_eth0_pll_data.pll_10 = 0x00001313;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(1);
ath79_init_mac(mac, art, 0x10);
ap91_pci_init(art + OM5P_PCI_CALDATA_OFFSET, mac);
}
static void __init db120_vhyfi_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_gpio_output_select(DB120_VHYFI_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_vhyfi_leds_gpio),
db120_vhyfi_leds_gpio);
ath79_register_gpio_keys_polled(-1, DB120_VHYFI_KEYS_POLL_INTERVAL,
ARRAY_SIZE(db120_vhyfi_gpio_keys),
db120_vhyfi_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + DB120_VHYFI_WMAC_CALDATA_OFFSET, NULL);
ap91_pci_init(art + DB120_VHYFI_PCIE_CALDATA_OFFSET, NULL);
db120_vhyfi_gmac_setup();
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_VHYFI_MAC0_OFFSET, 0);
mdiobus_register_board_info(db120_vhyfi_mdio0_info,
ARRAY_SIZE(db120_vhyfi_mdio0_info));
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init dr344_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
dr34x_setup();
ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
gpio_set_value(DR344_GPIO_LED_LAN, 1);
ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
dr344_leds_gpio);
ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
ath79_register_mdio(1, 0x0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR34X_MAC1_OFFSET, 0);
ath79_register_eth(1);
}
static void __init cf_e320n_v2_setup(void)
{
cf_exxxn_common_setup(0x10000, CF_E320N_V2_GPIO_EXT_WDT);
cf_exxxn_qca953x_eth_setup();
/* Disable JTAG (enables GPIO0-3) */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_direction_select(CF_E320N_V2_GPIO_LED_LAN, true);
ath79_gpio_direction_select(CF_E320N_V2_GPIO_LED_WAN, true);
ath79_gpio_direction_select(CF_E320N_V2_GPIO_LED_WLAN, true);
ath79_gpio_output_select(CF_E320N_V2_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_LED_WAN, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_LED_WLAN, 0);
/* Enable GPIO function for GPIOs in J9 header */
ath79_gpio_output_select(CF_E320N_V2_GPIO_HEADER_J9_1, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_HEADER_J9_2, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_HEADER_J9_3, 0);
ath79_gpio_output_select(CF_E320N_V2_GPIO_HEADER_J9_4, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e320n_v2_leds_gpio),
cf_e320n_v2_leds_gpio);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e320n_v2_gpio_keys),
cf_e320n_v2_gpio_keys);
}
static void __init om2p_hs_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
/* make lan / wan leds software controllable */
ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
/* enable reset button */
ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN;
om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN;
ath79_register_m25p80(&om2p_lc_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
om2p_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
ath79_register_wmac(art, NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
}
static void __init cf_e5x0n_gpio_setup(void)
{
ath79_gpio_direction_select(CF_E5X0N_GPIO_LED_WAN, true);
ath79_gpio_output_select(CF_E5X0N_GPIO_LED_WAN, 0);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e320n_v2_gpio_keys),
cf_e320n_v2_gpio_keys);
}
static void __init cf_e380ac_v1v2_common_setup(unsigned long art_ofs)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f000000 + art_ofs);
cf_exxxn_common_setup(art_ofs, CF_E380AC_V1V2_GPIO_EXT_WDT);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(cf_e380ac_v1v2_mdio0_info,
ARRAY_SIZE(cf_e380ac_v1v2_mdio0_info));
/* LAN */
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_pll_data.pll_1000 = 0xbe000000;
ath79_eth0_pll_data.pll_100 = 0xb0000101;
ath79_eth0_pll_data.pll_10 = 0xb0001313;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
ap91_pci_init(mac + 0x5000, NULL);
/* Disable JTAG (enables GPIO0-3) */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_LAN, true);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_WLAN2G, true);
ath79_gpio_direction_select(CF_E380AC_V1V2_GPIO_LED_WLAN5G, true);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_WLAN2G, 0);
ath79_gpio_output_select(CF_E380AC_V1V2_GPIO_LED_WLAN5G, 0);
/* For J7-4 */
ath79_gpio_function_disable(AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e380ac_v1v2_gpio_keys),
cf_e380ac_v1v2_gpio_keys);
}
static void __init cf_e355ac_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1f010000);
/* Disable JTAG, enabling GPIOs 0-3 */
ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, 0);
cf_exxxn_common_setup(0x10000, CF_E355AC_GPIO_EXT_WDT);
cf_exxxn_qca953x_eth_setup();
ath79_gpio_output_select(CF_E355AC_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E355AC_GPIO_LED_WLAN2G, 0);
ath79_gpio_output_select(CF_E355AC_GPIO_LED_WLAN5G, 0);
ap91_pci_init(art + 0x5000, NULL);
ath79_register_gpio_keys_polled(1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e355ac_gpio_keys),
cf_e355ac_gpio_keys);
}
/*
* Init the mAP lite hardware (QCA953x).
* The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
* Trying to use GMAC0 in direct mode was unsucessful, so we're
* using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
* switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
*/
static void __init rbmapl_setup(void)
{
u32 flags = RBSPI_HAS_WLAN0;
if (!rbspi_platform_setup())
return;
rbspi_peripherals_setup(flags);
/* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
rbspi_network_setup(flags, 0, 1, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
/* mAP lite has a single reset button as gpio 16 */
rbspi_register_reset_button(RBMAPL_GPIO_BTN_RESET);
/* clear internal multiplexing */
ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
}
static void __init cap4200ag_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 mac[6];
ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_GREEN,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(CAP4200AG_GPIO_LED_LAN_AMBER,
AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cap4200ag_leds_gpio),
cap4200ag_leds_gpio);
ath79_register_gpio_keys_polled(-1, CAP4200AG_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cap4200ag_gpio_keys),
cap4200ag_gpio_keys);
ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -1);
ath79_wmac_disable_2ghz();
ath79_register_wmac(art + CAP4200AG_WMAC_CALDATA_OFFSET, mac);
ath79_init_mac(mac, art + CAP4200AG_MAC_OFFSET, -2);
ap91_pci_init(art + CAP4200AG_PCIE_CALDATA_OFFSET, mac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr,
art + CAP4200AG_MAC_OFFSET, -2);
/* GMAC0 is connected to an external PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
static void __init cus227_audio_setup(void)
{
u32 t;
/* Reset I2S internal controller */
t = ath79_reset_rr(AR71XX_RESET_REG_RESET_MODULE);
ath79_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | AR934X_RESET_I2S );
udelay(1);
/* GPIO configuration
Please note that the value in direction_output doesn't really matter
here as GPIOs are configured to relay internal data signal
*/
gpio_request(CUS227_GPIO_I2S_CLK, "I2S CLK");
ath79_gpio_output_select(CUS227_GPIO_I2S_CLK, AR934X_GPIO_OUT_MUX_I2S_CLK);
gpio_direction_output(CUS227_GPIO_I2S_CLK, 0);
gpio_request(CUS227_GPIO_I2S_WS, "I2S WS");
ath79_gpio_output_select(CUS227_GPIO_I2S_WS, AR934X_GPIO_OUT_MUX_I2S_WS);
gpio_direction_output(CUS227_GPIO_I2S_WS, 0);
gpio_request(CUS227_GPIO_I2S_SD, "I2S SD");
ath79_gpio_output_select(CUS227_GPIO_I2S_SD, AR934X_GPIO_OUT_MUX_I2S_SD);
gpio_direction_output(CUS227_GPIO_I2S_SD, 0);
gpio_request(CUS227_GPIO_I2S_MCLK, "I2S MCLK");
ath79_gpio_output_select(CUS227_GPIO_I2S_MCLK, AR934X_GPIO_OUT_MUX_I2S_MCK);
gpio_direction_output(CUS227_GPIO_I2S_MCLK, 0);
gpio_request(CUS227_GPIO_SPDIF_OUT, "SPDIF OUT");
ath79_gpio_output_select(CUS227_GPIO_SPDIF_OUT, AR934X_GPIO_OUT_MUX_SPDIF_OUT);
gpio_direction_output(CUS227_GPIO_SPDIF_OUT, 0);
gpio_request(CUS227_GPIO_I2S_MIC_SD, "I2S MIC_SD");
ath79_gpio_input_select(CUS227_GPIO_I2S_MIC_SD, AR934X_GPIO_IN_MUX_I2S_MIC_SD);
gpio_direction_input(CUS227_GPIO_I2S_MIC_SD);
/* Init stereo block registers in default configuration */
ath79_audio_setup();
}
static void __init cr5000_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
gpio_request_one(CR5000_GPIO_LED_POWER_ENABLE,
GPIOF_OUT_INIT_LOW, "Power LED enable");
ath79_gpio_output_select(CR5000_GPIO_LED_POWER_AMBER, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(CR5000_GPIO_LED_WLAN_2G, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(CR5000_GPIO_LED_WPS, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cr5000_leds_gpio),
cr5000_leds_gpio);
ath79_register_gpio_keys_polled(-1, CR5000_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cr5000_gpio_keys),
cr5000_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + CR5000_WMAC_CALDATA_OFFSET, art + CR5000_WMAC_MAC_OFFSET);
ap94_pci_init(NULL, NULL, NULL, art + CR5000_PCIE_MAC_OFFSET);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + CR5000_MAC0_OFFSET, 0);
mdiobus_register_board_info(cr5000_mdio0_info,
ARRAY_SIZE(cr5000_mdio0_info));
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
/*
* Init the mAP lite hardware.
* The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
* Trying to use GMAC0 in direct mode was unsucessful, so we're
* using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
* switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
*/
static void __init rbmapl_setup(void)
{
u32 flags = RBSPI_HAS_WLAN;
if (rbspi_platform_setup())
return;
rbspi_peripherals_setup(flags);
/* GMAC1 is HW MAC, WLAN MAC is HW MAC + 1 */
rbspi_network_setup(flags, 0, 1);
ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
/* mAP lite has a single reset button as gpio 16 */
ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
ARRAY_SIZE(rbspi_gpio_keys_reset16),
rbspi_gpio_keys_reset16);
/* clear internal multiplexing */
ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
}
static void __init apv5_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
//ath79_gpio_output_select(APV5_GPIO_LED_STATUS, AR934X_GPIO_OUT_GPIO);
//ath79_gpio_output_select(APV5_GPIO_LED_WLAN_5G, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(APV5_GPIO_LED_WLAN_2G, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(apv5_leds_gpio),
apv5_leds_gpio);
ath79_register_gpio_keys_polled(-1, APV5_KEYS_POLL_INTERVAL,
ARRAY_SIZE(apv5_gpio_keys),
apv5_gpio_keys);
ath79_register_usb();
//ath79_register_wmac(art + APV5_WMAC_CALDATA_OFFSET, NULL);
ath79_register_wmac(art + APV5_WMAC_CALDATA_OFFSET, NULL);
memcpy(art_for_qca98xx, art + APV5_QCA98XX_CALDATA_OFFSET, sizeof(art_for_qca98xx)); //zhaoyang1 modifies for loading qca98xx cal data 2015-02-06
ap91_pci_init(art + APV5_PCIE_CALDATA_OFFSET, NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + APV5_MAC0_OFFSET, 0);
mdiobus_register_board_info(apv5_mdio0_info,
ARRAY_SIZE(apv5_mdio0_info));
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
#if 0
/* GMAC1 is connected to the internal switch */
ath79_init_mac(ath79_eth1_data.mac_addr, art + APV5_MAC1_OFFSET, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
#endif
ath79_register_nfc();
}
static void __init om5p_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* make lan / wan leds software controllable */
ath79_gpio_output_select(OM5P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM5P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(&om5p_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5p_leds_gpio),
om5p_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM5P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om5p_gpio_keys),
om5p_gpio_keys);
ath79_init_mac(mac, art, 2);
ath79_register_wmac(art + OM5P_WMAC_CALDATA_OFFSET, mac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 1);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
}
static void __init dir825c1_setup(void)
{
ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB,
AR934X_GPIO_OUT_GPIO);
gpio_request_one(DIR825C1_GPIO_WAN_LED_ENABLE,
GPIOF_OUT_INIT_LOW, "WAN LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
dir825c1_leds_gpio);
ap9x_pci_setup_wmac_led_pin(0, 0);
dir825c1_generic_setup();
}
static void __init cf_e38xac_common_setup(unsigned long art_ofs)
{
cf_exxxn_common_setup(art_ofs, CF_E38XAC_GPIO_EXT_WDT);
ath79_register_pci();
/* Disable JTAG (enables GPIO0-3) */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_direction_select(CF_E38XAC_GPIO_LED_LAN, true);
ath79_gpio_direction_select(CF_E38XAC_GPIO_LED_WLAN2G, true);
ath79_gpio_direction_select(CF_E38XAC_GPIO_LED_WLAN5G, true);
ath79_gpio_output_select(CF_E38XAC_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E38XAC_GPIO_LED_WLAN2G, 0);
ath79_gpio_output_select(CF_E38XAC_GPIO_LED_WLAN5G, 0);
/* For J7-4 */
ath79_gpio_function_disable(AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e38xac_gpio_keys),
cf_e38xac_gpio_keys);
}
static void __init cf_e375ac_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f040000);
/* Disable JTAG, enabling GPIOs 0-3 */
ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE, 0);
cf_exxxn_common_setup(0x40000, CF_E375AC_GPIO_EXT_WDT);
ath79_gpio_output_select(CF_E375AC_GPIO_LED_LAN, 0);
ath79_gpio_output_select(CF_E375AC_GPIO_LED_WLAN2G, 0);
ath79_gpio_output_select(CF_E375AC_GPIO_LED_WLAN5G, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cf_e375ac_leds_gpio),
cf_e375ac_leds_gpio);
ath79_register_gpio_keys_polled(-1, CF_EXXXN_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cf_e375ac_gpio_keys),
cf_e375ac_gpio_keys);
platform_device_register(&ath79_mdio0_device);
mdiobus_register_board_info(cf_e375ac_mdio0_info,
ARRAY_SIZE(cf_e375ac_mdio0_info));
/* GMAC0 is connected to an AR8337 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_register_eth(0);
ath79_register_pci();
}
static void __init dir825c1_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1ffe0000);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
dir825c1_read_ascii_mac(mac1, mac + DIR825C1_MAC0_OFFSET);
dir825c1_read_ascii_mac(mac2, mac + DIR825C1_MAC1_OFFSET);
ath79_gpio_output_select(DIR825C1_GPIO_LED_BLUE_USB, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825c1_leds_gpio),
dir825c1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR825C1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir825c1_gpio_keys),
dir825c1_gpio_keys);
ap9x_pci_setup_wmac_led_pin(0, 13);
ap9x_pci_setup_wmac_led_pin(1, 32);
ath79_init_mac(tmpmac, mac1, 0);
ath79_register_wmac(art + DIR825C1_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac2, 0);
ap91_pci_init(art + DIR825C1_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(dir825c1_mdio0_info,
ARRAY_SIZE(dir825c1_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init mynet_rext_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(MYNET_REXT_ART_ADDR);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&mynet_rext_flash_data);
/* GPIO configuration from drivers/char/GPIO8.c */
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_POWER,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_WIFI,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY1,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY2,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_RF_QTY3,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_REXT_GPIO_LED_ETHERNET,
AR934X_GPIO_OUT_GPIO);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_rext_leds_gpio),
mynet_rext_leds_gpio);
ath79_register_gpio_keys_polled(-1, MYNET_REXT_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mynet_rext_gpio_keys),
mynet_rext_gpio_keys);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_RXD_DELAY |
AR934X_ETH_CFG_RDV_DELAY);
ath79_register_mdio(0, 0x0);
/* LAN */
mynet_rext_get_mac("et0macaddr=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to an external PHY on Port 4 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_pll_data.pll_1000 = 0x0e000000; /* athrs_mac.c */
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
/* WLAN */
mynet_rext_get_mac("wl0_hwaddr=", tmpmac);
ap91_pci_init(art + MYNET_REXT_WMAC_CALDATA_OFFSET, tmpmac);
}
static void __init wndr4300_setup(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(wndr4300_leds_gpio); i++)
ath79_gpio_output_select(wndr4300_leds_gpio[i].gpio,
AR934X_GPIO_OUT_GPIO);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wndr4300_leds_gpio),
wndr4300_leds_gpio);
ath79_register_gpio_keys_polled(-1, WNDR4300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wndr4300_gpio_keys),
wndr4300_gpio_keys);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wndr4300_mdio0_info,
ARRAY_SIZE(wndr4300_mdio0_info));
ath79_register_mdio(0, 0x0);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
ath79_register_nfc();
ath79_register_usb();
ath79_register_wmac_simple();
/* enable power for the USB port */
ap9x_pci_setup_wmac_gpio(0, BIT(WNDR4300_GPIO_USB_5V),
BIT(WNDR4300_GPIO_USB_5V));
ap91_pci_init_simple();
}
/*
* Setup the 911L hardware (AR9344).
*/
static void __init rb911l_setup(void)
{
const struct rb_info *info;
info = rbspi_platform_setup();
if (!info)
return;
if (!rb_has_hw_option(info, RB_HW_OPT_NO_NAND)) {
/*
* Old hardware revisions might be equipped with a NAND flash
* chip instead of the 16MiB SPI NOR device. Those boards are
* not supported at the moment, so throw a warning and skip
* the peripheral setup to avoid messing up the data in the
* flash chip.
*/
WARN(1, "The NAND flash on this board is not supported.\n");
} else {
rbspi_peripherals_setup(0);
}
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
rbspi_wlan_init(0, 1);
rbspi_register_reset_button(RB911L_GPIO_BTN_RESET);
/* Make the eth LED controllable by software. */
ath79_gpio_output_select(RB911L_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
ath79_register_leds_gpio(-1, ARRAY_SIZE(rb911l_leds), rb911l_leds);
}
static void __init reh132_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_gpio_output_select(REH132_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(reh132_leds_gpio),
reh132_leds_gpio);
ath79_register_gpio_keys_polled(-1, REH132_KEYS_POLL_INTERVAL,
ARRAY_SIZE(reh132_gpio_keys),
reh132_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + REH132_WMAC_CALDATA_OFFSET, NULL);
ap91_pci_init(art + REH132_PCIE_CALDATA_OFFSET, NULL);
reh132_gmac_setup();
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + REH132_MAC0_OFFSET, 0);
mdiobus_register_board_info(reh132_mdio0_info,
ARRAY_SIZE(reh132_mdio0_info));
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_init_mac(ath79_eth1_data.mac_addr, art + REH132_MAC1_OFFSET, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_100;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
}
static void __init tl_ap123_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* Disable JTAG, enabling GPIOs 0-3 */
/* Configure OBS4 line, for GPIO 4*/
ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
AR934X_GPIO_FUNC_CLK_OBS4_EN);
/* config gpio4 as normal gpio function */
ath79_gpio_output_select(TL_MR3420V2_GPIO_USB_POWER,
AR934X_GPIO_OUT_GPIO);
ath79_register_m25p80(&tl_wr841n_v8_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init wr2041n_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&wr2041n_flash_data);
/* Disable JTAG to enable GPIO 0-4 */
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wr2041n_leds_gpio),
wr2041n_leds_gpio);
ath79_register_gpio_keys_polled(-1, WR2041N_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wr2041n_gpio_keys),
wr2041n_gpio_keys);
ath79_init_mac(tmpmac, mac, 0);
ath79_register_wmac(art + WR2041N_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac, 1);
// try to setup wlan led pin
ath79_wmac_set_led_pin(WR2041N_GPIO_WMAC_LED_WLAN);
ap91_pci_init(art + WR2041N_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 2);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_gpio_output_select(WR2041N_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK3);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN3,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(WR2041N_GPIO_LED_LAN4,
AR934X_GPIO_OUT_LED_LINK0);
}
static void __init qihoo_c301_setup(void)
{
ath79_register_m25p80_multi(&flash);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(QIHOO_C301_GPIO_SPI_CS1,
AR934X_GPIO_OUT_SPI_CS1);
gpio_request_one(QIHOO_C301_GPIO_ETH_LEN_EN,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"Ethernet LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(qihoo_c301_leds_gpio),
qihoo_c301_leds_gpio);
ath79_register_gpio_keys_polled(-1, QIHOO_C301_KEYS_POLL_INTERVAL,
ARRAY_SIZE(qihoo_c301_gpio_keys),
qihoo_c301_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, QIHOO_C301_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, QIHOO_C301_GPIO_EXTERNAL_LNA1);
qihoo_c301_get_mac("wlan24mac=", wlan24mac);
ath79_register_pci();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* LAN */
qihoo_c301_get_mac("lanmac=", ath79_eth1_data.mac_addr);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
qihoo_c301_get_mac("wanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
gpio_request_one(QIHOO_C301_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
qihoo_c301_board = 1;
}
