static void __init wrtnode2q_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
wrtnode2q_gpio_led_setup();
ath79_register_pci();
ath79_register_usb();
ath79_register_wmac(art + WRTNODE2Q_WMAC_CALDATA_OFFSET, NULL);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + WRTNODE2Q_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + WRTNODE2Q_MAC0_OFFSET, 1);
/* LAN ports */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
/* WAN port */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
}
static void __init WPJ563_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(WPJ563_leds_gpio),
WPJ563_leds_gpio);
ath79_register_gpio_keys_polled(-1, WPJ563_KEYS_POLL_INTERVAL,
ARRAY_SIZE(WPJ563_gpio_keys),
WPJ563_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + WPJ563_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(WPJ563_mdio0_info,
ARRAY_SIZE(WPJ563_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ563_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ563_MAC1_OFFSET, 0);
/* GMAC0 is connected to an QCA8334 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
}
__init void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0,
u8 *cal_data1, u8 *mac_addr1)
{
if (cal_data0)
memcpy(ap9x_wmac0_data.eeprom_data, cal_data0,
sizeof(ap9x_wmac0_data.eeprom_data));
if (cal_data1)
memcpy(ap9x_wmac1_data.eeprom_data, cal_data1,
sizeof(ap9x_wmac1_data.eeprom_data));
if (mac_addr0) {
memcpy(ap9x_wmac0_mac, mac_addr0, sizeof(ap9x_wmac0_mac));
ap9x_wmac0_data.macaddr = ap9x_wmac0_mac;
}
if (mac_addr1) {
memcpy(ap9x_wmac1_mac, mac_addr1, sizeof(ap9x_wmac1_mac));
ap9x_wmac1_data.macaddr = ap9x_wmac1_mac;
}
ath79_pci_set_plat_dev_init(ap94_pci_plat_dev_init);
ath79_register_pci();
pci_enable_ath9k_fixup(17, ap9x_wmac0_data.eeprom_data);
pci_enable_ath9k_fixup(18, ap9x_wmac1_data.eeprom_data);
}
static void __init tl_ap151_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f00fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&tl_wdr6500_v2_flash_data);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
/* WAN */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* LAN */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.speed = SPEED_1000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(ee + TL_WDR6500_V2_WMAC_CALDATA_OFFSET, tmpmac);
ath79_register_pci();
ath79_register_usb();
}
static void __init lima_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1f080000);
ath79_register_m25p80(NULL);
ath79_register_gpio_keys_polled(-1, LIMA_KEYS_POLL_INTERVAL,
ARRAY_SIZE(lima_gpio_keys),
lima_gpio_keys);
ath79_setup_ar933x_phy4_switch(true, true);
ath79_init_mac(ath79_eth0_data.mac_addr, art + LIMA_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + LIMA_MAC1_OFFSET, 0);
ath79_register_mdio(0, ~LIMA_ETH_PHYS);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask |= BIT(0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_mask = BIT(1);
ath79_register_eth(1);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_eth(0);
ath79_register_wmac(art + LIMA_CALDATA_OFFSET, NULL);
ath79_register_usb();
ath79_register_pci();
}
static void __init alfa_ap96_init(void)
{
alfa_ap96_gpio_setup();
ath79_register_mdio(0, ~ALFA_AP96_MDIO_PHYMASK);
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = ALFA_AP96_WAN_PHYMASK;
ath79_eth1_pll_data.pll_1000 = 0x110000;
ath79_register_eth(0);
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = ALFA_AP96_LAN_PHYMASK;
ath79_eth1_pll_data.pll_1000 = 0x110000;
ath79_register_eth(1);
ath79_register_pci();
ath79_register_spi(&alfa_ap96_spi_data, alfa_ap96_spi_info,
ARRAY_SIZE(alfa_ap96_spi_info));
ath79_register_gpio_keys_polled(-1, ALFA_AP96_KEYS_POLL_INTERVAL,
ARRAY_SIZE(alfa_ap96_gpio_keys),
alfa_ap96_gpio_keys);
ath79_register_usb();
}
static void __init ja76pf2_init(void)
{
ath79_register_m25p80(&ja76pf_flash_data);
ath79_register_mdio(0, ~JA76PF2_MDIO_PHYMASK);
/* MAC0 is connected to the CPU port of the AR8316 switch */
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
/* MAC1 is connected to the PHY4 of the AR8316 switch */
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = BIT(4);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf2_leds_gpio),
ja76pf2_leds_gpio);
ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ja76pf2_gpio_keys),
ja76pf2_gpio_keys);
ath79_register_pci();
}
static void __init ja76pf_init(void)
{
ath79_register_m25p80(&ja76pf_flash_data);
ath79_register_mdio(0, ~JA76PF_MDIO_PHYMASK);
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = JA76PF_LAN_PHYMASK;
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = JA76PF_WAN_PHYMASK;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_register_eth(1);
platform_device_register(&ja76pf_i2c_gpio_device);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ja76pf_leds_gpio),
ja76pf_leds_gpio);
ath79_register_gpio_keys_polled(-1, JA76PF_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ja76pf_gpio_keys),
ja76pf_gpio_keys);
ath79_register_usb();
ath79_register_pci();
}
static void __init om5p_acv2_setup(void)
{
u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
u8 mac[6];
/* power amplifier high power, 4.2V at RFFM4203/4503 instead of 3.3 */
ath79_gpio_function_enable(QCA955X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_DCDC, QCA955X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM5PACV2_GPIO_PA_HIGH, QCA955X_GPIO_OUT_GPIO);
gpio_request_one(OM5PACV2_GPIO_PA_DCDC, GPIOF_OUT_INIT_HIGH,
"PA DC/DC");
gpio_request_one(OM5PACV2_GPIO_PA_HIGH, GPIOF_OUT_INIT_HIGH, "PA HIGH");
/* temperature sensor */
platform_device_register(&om5pacv2_i2c_device);
i2c_register_board_info(0, om5pacv2_i2c_devs,
ARRAY_SIZE(om5pacv2_i2c_devs));
ath79_register_m25p80(&om5pacv2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om5pacv2_leds_gpio),
om5pacv2_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM5PACV2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om5pacv2_gpio_keys),
om5pacv2_gpio_keys);
ath79_init_mac(mac, art, 0x02);
ath79_register_wmac(art + OM5PACV2_WMAC_CALDATA_OFFSET, mac);
om5p_acv2_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN, 2, 2, 0, 0);
ath79_register_mdio(0, 0x0);
ath79_register_mdio(1, 0x0);
mdiobus_register_board_info(om5pacv2_an_mdio0_info,
ARRAY_SIZE(om5pacv2_an_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art, 0x00);
ath79_init_mac(ath79_eth1_data.mac_addr, art, 0x01);
/* GMAC0 is connected to the PHY4 */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_pll_data.pll_1000 = 0x82000101;
ath79_eth0_pll_data.pll_100 = 0x80000101;
ath79_eth0_pll_data.pll_10 = 0x80001313;
ath79_register_eth(0);
/* GMAC1 is connected to MDIO1 in SGMII mode */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_eth1_data.phy_mask = BIT(1);
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_eth1_pll_data.pll_100 = 0x80000101;
ath79_eth1_pll_data.pll_10 = 0x80001313;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init e600g_v2_common_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f050400);
u8 *art = (u8 *) KSEG1ADDR(0x1f061000);
ath79_register_m25p80(NULL);
ath79_setup_ar933x_phy4_switch(false, false);
ath79_register_mdio(0, 0x0);
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = 0xfe;
/* LAN */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.speed = SPEED_100;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* WAN */
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.phy_mask = BIT(0);
ath79_eth1_data.speed = SPEED_1000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
ath79_register_pci();
ath79_register_usb();
ath79_register_wmac(art, NULL);
}
static void __init k2t_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(k2t_leds_gpio),
k2t_leds_gpio);
ath79_register_gpio_keys_polled(-1, K2T_KEYS_POLL_INTERVAL,
ARRAY_SIZE(k2t_gpio_keys),
k2t_gpio_keys);
ath79_register_usb();
platform_device_register(&ath79_mdio0_device);
mdiobus_register_board_info(k2t_mdio0_info,
ARRAY_SIZE(k2t_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art + K2T_MAC0_OFFSET, 0);
/* GMAC0 is connected to an AR8337 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
ath79_register_wmac_simple();
ath79_register_pci();
}
static void __init ap113_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(&ap113_flash_data);
ath79_register_mdio(0, ~BIT(0));
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_register_eth(0);
ath79_register_gpio_keys_polled(-1, AP113_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap113_gpio_keys),
ap113_gpio_keys);
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap113_leds_gpio),
ap113_leds_gpio);
ath79_register_pci();
ath79_register_usb();
}
static void __init dr344_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
ath79_register_m25p80(NULL);
ath79_gpio_direction_select(DR344_GPIO_LED_STATUS, true);
gpio_set_value(DR344_GPIO_LED_STATUS, 1);
ath79_gpio_output_select(DR344_GPIO_LED_STATUS, 0);
ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
gpio_set_value(DR344_GPIO_LED_LAN, 1);
ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
dr344_leds_gpio);
ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dr344_gpio_keys),
dr344_gpio_keys);
ath79_register_usb();
ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(dr344_mdio0_info,
ARRAY_SIZE(dr344_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
/* GMAC0 is connected to an AR8035 Gbps PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x02000000;
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_register_eth(1);
}
static void __init ubnt_xm_pci_init(void)
{
memcpy(ubnt_xm_eeprom_data.eeprom_data, UBNT_XM_EEPROM_ADDR,
sizeof(ubnt_xm_eeprom_data.eeprom_data));
ath79_pci_set_plat_dev_init(ubnt_xm_pci_plat_dev_init);
ath79_register_pci();
}
static void __init ap136_pci_init(u8 *eeprom)
{
memcpy(ap136_ath9k_data.eeprom_data, eeprom,
sizeof(ap136_ath9k_data.eeprom_data));
ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
ath79_register_pci();
}
static void __init common_setup(bool pcie_slot)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
ath79_register_m25p80(&archer_c7_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
archer_c7_leds_gpio);
ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c7_gpio_keys),
archer_c7_gpio_keys);
tplink_register_builtin_wmac1(ARCHER_C7_WMAC_CALDATA_OFFSET, mac, -1);
if (pcie_slot) {
ath79_register_pci();
} else {
ap9x_pci_setup_wmac_led_pin(0, 0);
tplink_register_ap91_wmac2(ARCHER_C7_PCIE_CALDATA_OFFSET, mac, 2);
}
mdiobus_register_board_info(archer_c7_mdio0_info,
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
}
/*
* AP135-020 is similar to AP136-020, any future AP135 specific init
* code can be added here.
*/
static void __init ap135_020_setup(void)
{
ap136_leds_gpio[0].name = "ap135:green:status";
ap136_leds_gpio[1].name = "ap135:red:status";
ap136_leds_gpio[2].name = "ap135:green:wps";
ap136_leds_gpio[3].name = "ap135:red:wps";
ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
ap136_leds_gpio[5].name = "ap135:red:usb";
ap136_020_common_setup();
ath79_register_pci();
}
static void __init wdr7500_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(&wdr7500_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr7500_leds_gpio),
wdr7500_leds_gpio);
ath79_register_gpio_keys_polled(-1, WDR7500_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wdr7500_gpio_keys),
wdr7500_gpio_keys);
gpio_request_one(WDR7500_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(WDR7500_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
ath79_register_nfc();
ath79_register_wmac(art + WDR7500_WMAC_CALDATA_OFFSET, NULL);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + WDR7500_MAC0_OFFSET, 0);
mdiobus_register_board_info(wdr7500_mdio0_info,
ARRAY_SIZE(wdr7500_mdio0_info));
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init archer_c7_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&archer_c7_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
archer_c7_leds_gpio);
ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
ARRAY_SIZE(archer_c7_gpio_keys),
archer_c7_gpio_keys);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac);
ath79_register_pci();
mdiobus_register_board_info(archer_c7_mdio0_info,
ARRAY_SIZE(archer_c7_mdio0_info));
ath79_register_mdio(0, 0x0);
archer_c7_gmac_setup();
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
}
static void __init pb44_init(void)
{
i2c_register_board_info(0, pb44_i2c_board_info,
ARRAY_SIZE(pb44_i2c_board_info));
platform_device_register(&pb44_i2c_gpio_device);
ath79_register_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio),
pb44_leds_gpio);
ath79_register_gpio_keys_polled(-1, PB44_KEYS_POLL_INTERVAL,
ARRAY_SIZE(pb44_gpio_keys),
pb44_gpio_keys);
ath79_register_spi(&pb44_spi_data, pb44_spi_info,
ARRAY_SIZE(pb44_spi_info));
ath79_register_usb();
ath79_register_pci();
}
__init void ap91_pci_init(u8 *cal_data, u8 *mac_addr)
{
if (cal_data)
memcpy(ap9x_wmac0_data.eeprom_data, cal_data,
sizeof(ap9x_wmac0_data.eeprom_data));
if (mac_addr) {
memcpy(ap9x_wmac0_mac, mac_addr, sizeof(ap9x_wmac0_mac));
ap9x_wmac0_data.macaddr = ap9x_wmac0_mac;
}
pci_enable_ath9k_fixup(0, ap9x_wmac0_data.eeprom_data);
ath79_pci_set_plat_dev_init(ap91_pci_plat_dev_init);
ath79_register_pci();
}
static void __init rb922gs_setup(void)
{
const struct rb_info *info;
char buf[64];
info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000);
if (!info)
return;
scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s",
(info->board_name) ? info->board_name : "");
mips_set_machine_name(buf);
rb922gs_init_partitions(info);
ath79_register_m25p80(&rb922gs_spi_flash_data);
rb922gs_nand_init();
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(rb922gs_mdio0_info,
ARRAY_SIZE(rb922gs_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(RB922_PHY_ADDR);
ath79_eth0_pll_data.pll_10 = 0x81001313;
ath79_eth0_pll_data.pll_100 = 0x81000101;
ath79_eth0_pll_data.pll_1000 = 0x8f000000;
ath79_register_eth(0);
ath79_register_pci();
ath79_register_leds_gpio(-1, ARRAY_SIZE(rb922gs_leds), rb922gs_leds);
ath79_register_gpio_keys_polled(-1, RB922_KEYS_POLL_INTERVAL,
ARRAY_SIZE(rb922gs_gpio_keys),
rb922gs_gpio_keys);
/* NOTE:
* This only supports the RB911G-5HPacD board for now. For other boards
* more devices must be registered based on the hardware options which
* can be found in the hardware configuration of RouterBOOT.
*/
}
static void __init dw33d_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dw33d_leds_gpio),
dw33d_leds_gpio);
ath79_register_gpio_keys_polled(-1, DW33D_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dw33d_gpio_keys),
dw33d_gpio_keys);
ath79_register_usb();
ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_HW);
ath79_register_nfc();
ath79_register_pci();
ath79_register_wmac(art + DW33D_WMAC_CALDATA_OFFSET, art + DW33D_WMAC_OFFSET);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + DW33D_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + DW33D_MAC1_OFFSET, 0);
mdiobus_register_board_info(dw33d_mdio0_info,
ARRAY_SIZE(dw33d_mdio0_info));
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_register_eth(0);
/* GMAC1 is connected tot eh SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_register_eth(1);
}
static void __init wpj344_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj344_leds_gpio),
wpj344_leds_gpio);
ath79_register_gpio_keys_polled(-1, WPJ344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wpj344_gpio_keys),
wpj344_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + WPJ344_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(wpj344_mdio0_info,
ARRAY_SIZE(wpj344_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, art + WPJ344_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, art + WPJ344_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
/* GMAC0 is connected to an AR8327 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_register_eth(1);
}
/*
* Common peripherals init routine for all SPI NOR devices.
* Sets SPI and USB.
*/
static void __init rbspi_peripherals_setup(u32 flags)
{
unsigned spi_n;
if (flags & RBSPI_HAS_SSR)
spi_n = ARRAY_SIZE(rbspi_spi_info);
else
spi_n = 1; /* only one device on bus0 */
rbspi_ath79_spi_data.num_chipselect = spi_n;
rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
if (flags & RBSPI_HAS_USB)
ath79_register_usb();
if (flags & RBSPI_HAS_PCI)
ath79_register_pci();
}
static void __init gl_ar300m_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_register_spi(&gl_ar300m_spi_data, gl_ar300m_spi_info, 2);
/* register gpio LEDs and keys */
ath79_register_leds_gpio(-1, ARRAY_SIZE(gl_ar300m_leds_gpio),
gl_ar300m_leds_gpio);
ath79_register_gpio_keys_polled(-1, GL_AR300M_KEYS_POLL_INTERVAL,
ARRAY_SIZE(gl_ar300m_gpio_keys),
gl_ar300m_gpio_keys);
ath79_register_mdio(0, 0x0);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, art + GL_AR300M_MAC0_OFFSET, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.speed = SPEED_100;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(4);
ath79_register_eth(0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, art + GL_AR300M_MAC1_OFFSET, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_switch_data.phy_poll_mask |= BIT(4);
ath79_switch_data.phy4_mii_en = 1;
ath79_register_eth(1);
ath79_init_mac(tmpmac, art + GL_AR300M_WMAC_CALDATA_OFFSET + 2, 0);
ath79_register_wmac(art + GL_AR300M_WMAC_CALDATA_OFFSET, tmpmac);
/* enable usb */
ath79_register_usb();
/* enable pci */
ath79_register_pci();
}
static void __init sc1750_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(sc1750_leds_gpio),
sc1750_leds_gpio);
ath79_register_gpio_keys_polled(-1, SC1750_KEYS_POLL_INTERVAL,
ARRAY_SIZE(sc1750_gpio_keys),
sc1750_gpio_keys);
ath79_register_usb();
ath79_register_nfc();
ath79_register_wmac(art + SC1750_WMAC_CALDATA_OFFSET, NULL);
ath79_register_mdio(0, 0);
mdiobus_register_board_info(sc1750_mdio0_info,
ARRAY_SIZE(sc1750_mdio0_info));
ath79_init_mac(ath79_eth0_data.mac_addr, art + SC1750_MAC0_OFFSET, 0);
ath79_eth0_pll_data.pll_1000 = 0xa6000101;
ath79_eth0_pll_data.pll_100 = 0xa4000101;
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = 0xF;
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
ath79_register_pci();
}
static void __init wpe72_setup(void)
{
ath79_register_m25p80(&wpe72_flash_data);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 1);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_usb();
ath79_register_pci();
ath79_register_leds_gpio(-1, ARRAY_SIZE(wpe72_leds_gpio),
wpe72_leds_gpio);
ath79_register_gpio_keys_polled(-1, WPE72_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wpe72_gpio_keys),
wpe72_gpio_keys);
}
static void __init jwap230_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(jwap230_leds_gpio),
jwap230_leds_gpio);
mdiobus_register_board_info(jwap230_mdio0_info,
ARRAY_SIZE(jwap230_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* QCA9558 GMAC0 is connected to RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0xa6000000;
ath79_init_mac(ath79_eth0_data.mac_addr, art + JWAP230_MAC0_OFFSET, 0);
ath79_register_eth(0);
/* QCA9558 GMAC1 is connected to SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, art + JWAP230_MAC1_OFFSET, 0);
ath79_register_eth(1);
ath79_register_wmac(art + JWAP230_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
ath79_register_usb();
}
static void __init wpj342_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj342_leds_gpio),
wpj342_leds_gpio);
ath79_register_gpio_keys_polled(-1, WPJ342_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wpj342_gpio_keys),
wpj342_gpio_keys);
ath79_register_usb();
ath79_register_wmac(art + WPJ342_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(wpj342_mdio0_info,
ARRAY_SIZE(wpj342_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ342_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ342_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0);
/* GMAC0 is connected to an AR8236 switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
}
