static void __init dr344_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
dr34x_setup();
ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
gpio_set_value(DR344_GPIO_LED_LAN, 1);
ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
dr344_leds_gpio);
ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
ath79_register_mdio(1, 0x0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR34X_MAC1_OFFSET, 0);
ath79_register_eth(1);
}
static void __init cpe510_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f830008);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
/* Disable JTAG, enabling GPIOs 0-3 */
/* Configure OBS4 line, for GPIO 4*/
ath79_gpio_function_setup(AR934X_GPIO_FUNC_JTAG_DISABLE,
AR934X_GPIO_FUNC_CLK_OBS4_EN);
ath79_register_leds_gpio(-1, ARRAY_SIZE(cpe510_leds_gpio),
cpe510_leds_gpio);
ath79_register_gpio_keys_polled(1, CPE510_KEYS_POLL_INTERVAL,
ARRAY_SIZE(cpe510_gpio_keys),
cpe510_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, CPE510_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, CPE510_GPIO_EXTERNAL_LNA1);
ath79_register_m25p80(NULL);
ath79_register_mdio(1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init dr344_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *mac = (u8 *) KSEG1ADDR(0x1f03f810);
ath79_register_m25p80(NULL);
ath79_gpio_direction_select(DR344_GPIO_LED_STATUS, true);
gpio_set_value(DR344_GPIO_LED_STATUS, 1);
ath79_gpio_output_select(DR344_GPIO_LED_STATUS, 0);
ath79_gpio_direction_select(DR344_GPIO_LED_LAN, true);
gpio_set_value(DR344_GPIO_LED_LAN, 1);
ath79_gpio_output_select(DR344_GPIO_LED_LAN, 0);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dr344_leds_gpio),
dr344_leds_gpio);
ath79_register_gpio_keys_polled(-1, DR344_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dr344_gpio_keys),
dr344_gpio_keys);
ath79_register_usb();
ath79_wmac_set_ext_lna_gpio(0, DR344_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, DR344_GPIO_EXTERNAL_LNA1);
ath79_register_wmac(art + DR344_WMAC_CALDATA_OFFSET, NULL);
ath79_register_pci();
mdiobus_register_board_info(dr344_mdio0_info,
ARRAY_SIZE(dr344_mdio0_info));
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac + DR344_MAC0_OFFSET, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac + DR344_MAC1_OFFSET, 0);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
/* GMAC0 is connected to an AR8035 Gbps PHY */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x02000000;
ath79_eth0_pll_data.pll_100 = 0x0101;
ath79_eth0_pll_data.pll_10 = 0x1313;
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(0);
ath79_register_eth(1);
}
static void __init wdr4300_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&wdr4300_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio),
wdr4300_leds_gpio);
ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wdr4300_gpio_keys),
wdr4300_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, WDR4300_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, WDR4300_GPIO_EXTERNAL_LNA1);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac, 0);
ap9x_pci_setup_wmac_led_pin(0, 0);
ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wdr4300_mdio0_info,
ARRAY_SIZE(wdr4300_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
gpio_request_one(WDR4300_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(WDR4300_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
}
static void __init mynet_n750_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(NULL);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n750_leds_gpio),
mynet_n750_leds_gpio);
ath79_register_gpio_keys_polled(-1, MYNET_N750_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mynet_n750_gpio_keys),
mynet_n750_gpio_keys);
/*
* Control signal for external LNAs 0 and 1
* Taken from GPL bootloader source:
* board/ar7240/db12x/alpha_gpio.c
*/
ath79_wmac_set_ext_lna_gpio(0, MYNET_N750_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, MYNET_N750_GPIO_EXTERNAL_LNA1);
mynet_n750_get_mac("wlan24mac=", tmpmac);
ath79_register_wmac(art + MYNET_N750_WMAC_CALDATA_OFFSET, tmpmac);
mynet_n750_get_mac("wlan5mac=", tmpmac);
ap91_pci_init(art + MYNET_N750_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(mynet_n750_mdio0_info,
ARRAY_SIZE(mynet_n750_mdio0_info));
ath79_mdio0_data.reset = mynet_n750_mdio_fixup;
ath79_register_mdio(0, 0x0);
mynet_n750_get_mac("lanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
ath79_register_usb();
}
static void __init qihoo_c301_setup(void)
{
ath79_register_m25p80_multi(&flash);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(QIHOO_C301_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(QIHOO_C301_GPIO_SPI_CS1,
AR934X_GPIO_OUT_SPI_CS1);
gpio_request_one(QIHOO_C301_GPIO_ETH_LEN_EN,
GPIOF_OUT_INIT_LOW | GPIOF_EXPORT_DIR_FIXED,
"Ethernet LED enable");
ath79_register_leds_gpio(-1, ARRAY_SIZE(qihoo_c301_leds_gpio),
qihoo_c301_leds_gpio);
ath79_register_gpio_keys_polled(-1, QIHOO_C301_KEYS_POLL_INTERVAL,
ARRAY_SIZE(qihoo_c301_gpio_keys),
qihoo_c301_gpio_keys);
ath79_wmac_set_ext_lna_gpio(0, QIHOO_C301_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, QIHOO_C301_GPIO_EXTERNAL_LNA1);
qihoo_c301_get_mac("wlan24mac=", wlan24mac);
ath79_register_pci();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* LAN */
qihoo_c301_get_mac("lanmac=", ath79_eth1_data.mac_addr);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
qihoo_c301_get_mac("wanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
gpio_request_one(QIHOO_C301_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
qihoo_c301_board = 1;
}
static void __init mynet_n600_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(NULL);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN1,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN2,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN3,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_LAN4,
AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(MYNET_N600_GPIO_LED_INTERNET,
AR934X_GPIO_OUT_GPIO);
ath79_register_leds_gpio(-1, ARRAY_SIZE(mynet_n600_leds_gpio),
mynet_n600_leds_gpio);
ath79_register_gpio_keys_polled(-1, MYNET_N600_KEYS_POLL_INTERVAL,
ARRAY_SIZE(mynet_n600_gpio_keys),
mynet_n600_gpio_keys);
/*
* Control signal for external LNAs 0 and 1
* Taken from GPL bootloader source:
* board/ar7240/db12x/alpha_gpio.c
*/
ath79_wmac_set_ext_lna_gpio(0, MYNET_N600_GPIO_EXTERNAL_LNA0);
ath79_wmac_set_ext_lna_gpio(1, MYNET_N600_GPIO_EXTERNAL_LNA1);
mynet_n600_get_mac("wlan24mac=", tmpmac);
ath79_register_wmac(art + MYNET_N600_WMAC_CALDATA_OFFSET, tmpmac);
mynet_n600_get_mac("wlan5mac=", tmpmac);
ap91_pci_init(art + MYNET_N600_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE |
AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
/* LAN */
mynet_n600_get_mac("lanmac=", ath79_eth1_data.mac_addr);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
mynet_n600_get_mac("wanmac=", ath79_eth0_data.mac_addr);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = MYNET_N600_WAN_PHY_MASK;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = MYNET_N600_WAN_PHY_MASK;
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_register_usb();
}
