コード例 #1
0
int
main(int argc, char *argv[])
{
	struct ath_diag atd;
	const char *ifname;
	u_int32_t *data;
	u_int32_t *dp, *ep;
	int what, c, s, i;

	s = socket(AF_INET, SOCK_DGRAM, 0);
	if (s < 0)
		err(1, "socket");
	ifname = getenv("ATH");
	if (!ifname)
		ifname = ATH_DEFAULT;

	what = 0;
	state.show_addrs = 0;
	state.show_names = 1;
	while ((c = getopt(argc, argv, "i:aAbdkmNqxz")) != -1)
		switch (c) {
		case 'a':
			what |= DUMP_ALL;
			break;
		case 'A':
			state.show_addrs = 1;
			break;
		case 'b':
			what |= DUMP_BASEBAND;
			break;
		case 'd':
			what |= DUMP_DCU;
			break;
		case 'k':
			what |= DUMP_KEYCACHE;
			break;
		case 'i':
			ifname = optarg;
			break;
		case 'm':
			what |= DUMP_BASIC;
			break;
		case 'N':
			state.show_names = 0;
			break;
		case 'q':
			what |= DUMP_QCU;
			break;
		case 'x':
			what |= DUMP_XR;
			break;
		case 'z':
			what |= DUMP_INTERRUPT;
			break;
		default:
			usage();
			/*NOTREACHED*/
		}
	strncpy(atd.ad_name, ifname, sizeof (atd.ad_name));

	argc -= optind;
	argv += optind;
	if (what == 0)
		what = DUMP_BASIC;

	atd.ad_id = HAL_DIAG_REVS;
	atd.ad_out_data = (caddr_t) &state.revs;
	atd.ad_out_size = sizeof(state.revs);
	if (ioctl(s, SIOCGATHDIAG, &atd) < 0)
		err(1, atd.ad_name);

	if (ath_hal_setupregs(&atd, what) == 0)
		errx(-1, "no registers are known for this part "
		    "(devid 0x%x mac %d.%d phy %d)", state.revs.ah_devid,
		    state.revs.ah_macVersion, state.revs.ah_macRev,
		    state.revs.ah_phyRev);

	atd.ad_out_size = ath_hal_setupdiagregs((HAL_REGRANGE *) atd.ad_in_data,
		atd.ad_in_size / sizeof(HAL_REGRANGE));
	atd.ad_out_data = (caddr_t) malloc(atd.ad_out_size);
	if (atd.ad_out_data == NULL) {
		fprintf(stderr, "Cannot malloc output buffer, size %u\n",
			atd.ad_out_size);
		exit(-1);
	}
	atd.ad_id = HAL_DIAG_REGS | ATH_DIAG_IN | ATH_DIAG_DYN;
	if (ioctl(s, SIOCGATHDIAG, &atd) < 0)
		err(1, atd.ad_name);

	/*
	 * Expand register data into global space that can be
	 * indexed directly by register offset.
	 */
	dp = (u_int32_t *)atd.ad_out_data;
	ep = (u_int32_t *)(atd.ad_out_data + atd.ad_out_size);
	while (dp < ep) {
		u_int r = dp[0] >> 16;		/* start of range */
		u_int e = dp[0] & 0xffff;	/* end of range */
		dp++;
		/* convert offsets to indices */
		r >>= 2; e >>= 2;
		do {
			if (dp >= ep) {
				fprintf(stderr, "Warning, botched return data;"
					"register at offset 0x%x not present\n",
					r << 2);
				break;
			}
			state.regdata[r++] = *dp++;
		} while (r <= e);
	} 

	if (what & DUMP_BASIC)
		ath_hal_dumpregs(stdout, DUMP_BASIC);
	if ((what & DUMP_INTERRUPT) && ath_hal_anyregs(DUMP_INTERRUPT)) {
		if (what & DUMP_BASIC)
			putchar('\n');
		if (state.show_addrs)
			ath_hal_dumpregs(stdout, DUMP_INTERRUPT);
		else
			ath_hal_dumpint(stdout, what);
	}
	if ((what & DUMP_QCU) && ath_hal_anyregs(DUMP_QCU)) {
		if (what & (DUMP_BASIC|DUMP_INTERRUPT))
			putchar('\n');
		if (state.show_addrs)
			ath_hal_dumpregs(stdout, DUMP_QCU);
		else
			ath_hal_dumpqcu(stdout, what);
	}
	if ((what & DUMP_DCU) && ath_hal_anyregs(DUMP_DCU)) {
		if (what & (DUMP_BASIC|DUMP_INTERRUPT|DUMP_QCU))
			putchar('\n');
		if (state.show_addrs)
			ath_hal_dumpregs(stdout, DUMP_DCU);
		else
			ath_hal_dumpdcu(stdout, what);
	}
	if (what & DUMP_KEYCACHE) {
		if (state.show_addrs) {
			if (what & (DUMP_BASIC|DUMP_INTERRUPT|DUMP_QCU|DUMP_DCU))
				putchar('\n');
			ath_hal_dumpregs(stdout, DUMP_KEYCACHE);
		} else
			ath_hal_dumpkeycache(stdout, 128);
	}
	if (what & DUMP_BASEBAND) {
		if (what &~ DUMP_BASEBAND)
			fprintf(stdout, "\n");
		ath_hal_dumpbb(stdout, what);
	}
	return 0;
}
コード例 #2
0
ファイル: dumpregs_9300.c プロジェクト: jorneytu/wlan
void
ar9300DumpRegs(FILE *fd, int what)
{
#define N(a)    (sizeof(a) / sizeof(a[0]))
    static const HAL_REG regs[] = {
        /* NB: keep these sorted by address */
        { "CR",     AR_CR },
        { "HPRXDP", AR_HP_RXDP },
        { "LPRXDP", AR_LP_RXDP },
        { "CFG",    AR_CFG },
        { "IER",    AR_IER },
        { "TXCFG",  AR_TXCFG },
        { "RXCFG",  AR_RXCFG },
        { "MIBC",   AR_MIBC },
        { "TOPS",   AR_TOPS },
        { "RXNPTO", AR_RXNPTO },
        { "TXNPTO", AR_TXNPTO },
        { "RPGTO",  AR_RPGTO },
        { "MACMISC", AR_MACMISC },
        { "D_SIFS", AR_D_GBL_IFS_SIFS },
        { "D_SEQNUM", AR_D_SEQNUM },
        { "D_SLOT", AR_D_GBL_IFS_SLOT },
        { "D_EIFS", AR_D_GBL_IFS_EIFS },
        { "D_MISC", AR_D_GBL_IFS_MISC },
        { "D_TXPSE", AR_D_TXPSE },
        { "RC",     AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL) },
//      { "SCR",    AR_SCR },
//      { "INTPEND",    AR_INTPEND },
//      { "SFR",    AR_SFR },
//      { "PCICFG", AR_PCICFG },
//      { "GPIOCR", AR_GPIOCR },
        { "SREV",   AR9300_HOSTIF_OFFSET(HOST_INTF_SREV) },
        { "STA_ID0",    AR_STA_ID0 },
        { "STA_ID1",    AR_STA_ID1 },
        { "BSS_ID0",    AR_BSS_ID0 },
        { "BSS_ID1",    AR_BSS_ID1 },
        { "TIME_OUT",   AR_TIME_OUT },
        { "RSSI_THR",   AR_RSSI_THR },
        { "USEC",   AR_USEC },
//      { "BEACON", AR_BEACON },
//      { "CFP_PER",    AR_CFP_PERIOD },
//      { "TIMER0", AR_TIMER0 },
//      { "TIMER1", AR_TIMER1 },
//      { "TIMER2", AR_TIMER2 },
//      { "TIMER3", AR_TIMER3 },
//      { "CFP_DUR",    AR_CFP_DUR },
        { "RX_FILTR",   AR_RX_FILTER },
        { "MCAST_0",    AR_MCAST_FIL0 },
        { "MCAST_1",    AR_MCAST_FIL1 },
        { "DIAG_SW",    AR_DIAG_SW },
        { "TSF_L32",    AR_TSF_L32 },
        { "TSF_U32",    AR_TSF_U32 },
        { "TST_ADAC",   AR_TST_ADDAC },
        { "DEF_ANT",    AR_DEF_ANTENNA },
        { "LAST_TST",   AR_LAST_TSTP },
        { "NAV",    AR_NAV },
        { "RTS_OK",     AR_RTS_OK },
        { "RTS_FAIL",   AR_RTS_FAIL },
        { "ACK_FAIL",   AR_ACK_FAIL },
        { "FCS_FAIL",   AR_FCS_FAIL },
        { "BEAC_CNT",   AR_BEACON_CNT },
#ifdef AH_SUPPORT_XR
        { "XRMODE", AR_XRMODE },
        { "XRDEL",  AR_XRDEL },
        { "XRTO",   AR_XRTO },
        { "XRCRP",  AR_XRCRP },
        { "XRSTMP", AR_XRSTMP },
#endif /* AH_SUPPORT_XR */
        { "SLEEP1", AR_SLEEP1 },
        { "SLEEP2", AR_SLEEP2 },
//      { "SLEEP3", AR_SLEEP3 },
        { "BSSMSKL",    AR_BSSMSKL },
        { "BSSMSKU",    AR_BSSMSKU },
        { "TPC",    AR_TPC },
        { "TFCNT",  AR_TFCNT },
        { "RFCNT",  AR_RFCNT },
        { "RCCNT",  AR_RCCNT },
        { "CCCNT",  AR_CCCNT },
//      { "NOACK",  AR_NOACK },
        { "PHY_ERR",    AR_PHY_ERR },
//      { "QOSCTL", AR_QOS_CONTROL },
//      { "QOSSEL", AR_QOS_SELECT },
//      { "MISCMODE",   AR_MISC_MODE },
//      { "FILTOFDM",   AR_FILTOFDM },
//      { "FILTCCK",    AR_FILTCCK },
//      { "PHYCNT1",    AR_PHYCNT1 },
//      { "PHYCMSK1",   AR_PHYCNTMASK1 },
//      { "PHYCNT2",    AR_PHYCNT2 },
//      { "PHYCMSK2",   AR_PHYCNTMASK2 },
    };
    int i;
    u_int32_t v;

    if (what & DUMP_BASIC) {
        ath_hal_dumpregs(fd, regs, N(regs));
    }
    if (what & DUMP_INTERRUPT) {
        /* Interrupt registers */
        if (what & DUMP_BASIC)
            fprintf(fd, "\n");
        fprintf(fd, "IMR: %08x S0 %08x S1 %08x S2 %08x S3 %08x S4 %08x\n"
            , OS_REG_READ(ah, AR_IMR)
            , OS_REG_READ(ah, AR_IMR_S0)
            , OS_REG_READ(ah, AR_IMR_S1)
            , OS_REG_READ(ah, AR_IMR_S2)
            , OS_REG_READ(ah, AR_IMR_S3)
            , OS_REG_READ(ah, AR_IMR_S4)
        );
        fprintf(fd, "ISR: %08x S0 %08x S1 %08x S2 %08x S3 %08x S4 %08x\n"
            , OS_REG_READ(ah, AR_ISR)
            , OS_REG_READ(ah, AR_ISR_S0)
            , OS_REG_READ(ah, AR_ISR_S1)
            , OS_REG_READ(ah, AR_ISR_S2)
            , OS_REG_READ(ah, AR_ISR_S3)
            , OS_REG_READ(ah, AR_ISR_S4)
        );
    }
    if (what & DUMP_QCU) {
        /* QCU registers */
        if (what & (DUMP_BASIC|DUMP_INTERRUPT))
            fprintf(fd, "\n");
        fprintf(fd, "%-8s %08x  %-8s %08x  %-8s %08x\n"
            , "Q_TXE", OS_REG_READ(ah, AR_Q_TXE)
            , "Q_TXD", OS_REG_READ(ah, AR_Q_TXD)
            , "Q_RDYTIMSHD", OS_REG_READ(ah, AR_Q_RDYTIMESHDN)
        );
        fprintf(fd, "Q_ONESHOTARM_SC %08x  Q_ONESHOTARM_CC %08x\n"
            , OS_REG_READ(ah, AR_Q_ONESHOTARM_SC)
            , OS_REG_READ(ah, AR_Q_ONESHOTARM_CC)
        );
        for (i = 0; i < 10; i++)
            fprintf(fd, "Q[%u] TXDP %08x CBR %08x RDYT %08x MISC %08x STS %08x\n"
                , i
                , OS_REG_READ(ah, AR_QTXDP(i))
                , OS_REG_READ(ah, AR_QCBRCFG(i))
                , OS_REG_READ(ah, AR_QRDYTIMECFG(i))
                , OS_REG_READ(ah, AR_QMISC(i))
                , OS_REG_READ(ah, AR_QSTS(i))
            );
    }
    if (what & DUMP_DCU) {
        /* DCU registers */
        if (what & (DUMP_BASIC|DUMP_INTERRUPT|DUMP_QCU))
            fprintf(fd, "\n");
        for (i = 0; i < 10; i++)
            fprintf(fd, "D[%u] MASK %08x IFS %08x RTRY %08x CHNT %08x MISC %06x\n"
                , i
                , OS_REG_READ(ah, AR_DQCUMASK(i))
                , OS_REG_READ(ah, AR_DLCL_IFS(i))
                , OS_REG_READ(ah, AR_DRETRY_LIMIT(i))
                , OS_REG_READ(ah, AR_DCHNTIME(i))
                , OS_REG_READ(ah, AR_DMISC(i))
            );
    }
    for (i = 0; i < 10; i++) {
        u_int32_t f0 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x00));
        u_int32_t f1 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x40));
        u_int32_t f2 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x80));
        u_int32_t f3 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0xc0));
        if (f0 || f1 || f2 || f3)
            fprintf(fd,
                "D[%u] XMIT MASK %08x %08x %08x %08x\n",
                i, f0, f1, f2, f3);
    }
    if (what & DUMP_KEYCACHE)
        ath_hal_dumpkeycache(fd, 128,
            OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_CRPT_MIC_ENABLE);

    if (what & DUMP_BASEBAND) {
        int reg;
        if (what &~ DUMP_BASEBAND)
            fprintf(fd, "\n");

        for (reg = 0x9800; reg <= 0xa480; reg += 4) {
            printf("%X %.8X\n", reg, OS_REG_READ(ah, reg));
        }
#if 0
        ath_hal_dumprange(fd, 0x9800, 0x987c);
        ath_hal_dumprange(fd, 0x9900, 0x995c);
        ath_hal_dumprange(fd, 0x9c00, 0x9c1c);
        ath_hal_dumprange(fd, 0xa180, 0xa238);
#endif
    }

    if (what & DUMP_LA) {
        int reg;
        for (reg = AR_MAC_PCU_TRACE_REG_START, i = 0; reg < AR_MAC_PCU_TRACE_REG_END; reg += 16) {
            printf("0x%X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg, 
                   OS_REG_READ(ah, reg + 0),
                   OS_REG_READ(ah, reg + 4),
                   OS_REG_READ(ah, reg + 8),
                   OS_REG_READ(ah, reg + 12));
        }
    }
    if (what & DUMP_DMADBG) {
        int reg;
        for (reg = AR_DMADBG_0, i = 0; reg <= AR_DMADBG_7; reg += 4) {
            printf("0x%X: 0x%.8X\n", reg, OS_REG_READ(ah, reg));
        }
    }
#undef N
}