static void atl1e_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) { struct atl1e_adapter *adapter = netdev_priv(netdev); struct atl1e_hw *hw = &adapter->hw; u32 *regs_buff = p; u16 phy_data; memset(p, 0, AT_REGS_LEN * sizeof(u32)); regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; regs_buff[0] = AT_READ_REG(hw, REG_VPD_CAP); regs_buff[1] = AT_READ_REG(hw, REG_SPI_FLASH_CTRL); regs_buff[2] = AT_READ_REG(hw, REG_SPI_FLASH_CONFIG); regs_buff[3] = AT_READ_REG(hw, REG_TWSI_CTRL); regs_buff[4] = AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); regs_buff[5] = AT_READ_REG(hw, REG_MASTER_CTRL); regs_buff[6] = AT_READ_REG(hw, REG_MANUAL_TIMER_INIT); regs_buff[7] = AT_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); regs_buff[8] = AT_READ_REG(hw, REG_GPHY_CTRL); regs_buff[9] = AT_READ_REG(hw, REG_CMBDISDMA_TIMER); regs_buff[10] = AT_READ_REG(hw, REG_IDLE_STATUS); regs_buff[11] = AT_READ_REG(hw, REG_MDIO_CTRL); regs_buff[12] = AT_READ_REG(hw, REG_SERDES_LOCK); regs_buff[13] = AT_READ_REG(hw, REG_MAC_CTRL); regs_buff[14] = AT_READ_REG(hw, REG_MAC_IPG_IFG); regs_buff[15] = AT_READ_REG(hw, REG_MAC_STA_ADDR); regs_buff[16] = AT_READ_REG(hw, REG_MAC_STA_ADDR+4); regs_buff[17] = AT_READ_REG(hw, REG_RX_HASH_TABLE); regs_buff[18] = AT_READ_REG(hw, REG_RX_HASH_TABLE+4); regs_buff[19] = AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); regs_buff[20] = AT_READ_REG(hw, REG_MTU); regs_buff[21] = AT_READ_REG(hw, REG_WOL_CTRL); regs_buff[22] = AT_READ_REG(hw, REG_SRAM_TRD_ADDR); regs_buff[23] = AT_READ_REG(hw, REG_SRAM_TRD_LEN); regs_buff[24] = AT_READ_REG(hw, REG_SRAM_RXF_ADDR); regs_buff[25] = AT_READ_REG(hw, REG_SRAM_RXF_LEN); regs_buff[26] = AT_READ_REG(hw, REG_SRAM_TXF_ADDR); regs_buff[27] = AT_READ_REG(hw, REG_SRAM_TXF_LEN); regs_buff[28] = AT_READ_REG(hw, REG_SRAM_TCPH_ADDR); regs_buff[29] = AT_READ_REG(hw, REG_SRAM_PKTH_ADDR); atl1e_read_phy_reg(hw, MII_BMCR, &phy_data); regs_buff[73] = (u32)phy_data; atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); regs_buff[74] = (u32)phy_data; }
static void atl1e_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p) { struct atl1e_adapter *adapter = netdev_priv(netdev); struct atl1e_hw *hw = &adapter->hw; u32 *regs_buff = p; u16 phy_data; memset(p, 0, AT_REGS_LEN * sizeof(u32)); regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; regs_buff[0] = AT_READ_REG(hw, REG_VPD_CAP); regs_buff[1] = AT_READ_REG(hw, REG_SPI_FLASH_CTRL); regs_buff[2] = AT_READ_REG(hw, REG_SPI_FLASH_CONFIG); regs_buff[3] = AT_READ_REG(hw, REG_TWSI_CTRL); regs_buff[4] = AT_READ_REG(hw, REG_PCIE_DEV_MISC_CTRL); regs_buff[5] = AT_READ_REG(hw, REG_MASTER_CTRL); regs_buff[6] = AT_READ_REG(hw, REG_MANUAL_TIMER_INIT); regs_buff[7] = AT_READ_REG(hw, REG_IRQ_MODU_TIMER_INIT); regs_buff[8] = AT_READ_REG(hw, REG_GPHY_CTRL); regs_buff[9] = AT_READ_REG(hw, REG_CMBDISDMA_TIMER); regs_buff[10] = AT_READ_REG(hw, REG_IDLE_STATUS); regs_buff[11] = AT_READ_REG(hw, REG_MDIO_CTRL); regs_buff[12] = AT_READ_REG(hw, REG_SERDES_LOCK); regs_buff[13] = AT_READ_REG(hw, REG_MAC_CTRL); regs_buff[14] = AT_READ_REG(hw, REG_MAC_IPG_IFG); regs_buff[15] = AT_READ_REG(hw, REG_MAC_STA_ADDR); regs_buff[16] = AT_READ_REG(hw, REG_MAC_STA_ADDR+4); regs_buff[17] = AT_READ_REG(hw, REG_RX_HASH_TABLE); regs_buff[18] = AT_READ_REG(hw, REG_RX_HASH_TABLE+4); regs_buff[19] = AT_READ_REG(hw, REG_MAC_HALF_DUPLX_CTRL); regs_buff[20] = AT_READ_REG(hw, REG_MTU); regs_buff[21] = AT_READ_REG(hw, REG_WOL_CTRL); regs_buff[22] = AT_READ_REG(hw, REG_SRAM_TRD_ADDR); regs_buff[23] = AT_READ_REG(hw, REG_SRAM_TRD_LEN); regs_buff[24] = AT_READ_REG(hw, REG_SRAM_RXF_ADDR); regs_buff[25] = AT_READ_REG(hw, REG_SRAM_RXF_LEN); regs_buff[26] = AT_READ_REG(hw, REG_SRAM_TXF_ADDR); regs_buff[27] = AT_READ_REG(hw, REG_SRAM_TXF_LEN); regs_buff[28] = AT_READ_REG(hw, REG_SRAM_TCPH_ADDR); regs_buff[29] = AT_READ_REG(hw, REG_SRAM_PKTH_ADDR); /* // description address regs_buff[30] = AT_READ_REG(hw, REG_DESC_BASE_ADDR_HI); regs_buff[31] = AT_READ_REG(hw, REG_TPD_BASE_ADDR_LO); regs_buff[32] = AT_READ_REG(hw, REG_TPD_RING_SIZE); regs_buff[33] = AT_READ_REG(hw, REG_HOST_RXF_HEAD); regs_buff[34] = AT_READ_REG(hw, REG_HOST_RXF_TAIL); regs_buff[35] = AT_READ_REG(hw, REG_HOST_RXRAM_SIZE); regs_buff[36] = AT_READ_REG(hw, REG_HOST_RXF1_HEAD); regs_buff[37] = AT_READ_REG(hw, REG_HOST_RXF1_TAIL); regs_buff[38] = AT_READ_REG(hw, REG_HOST_RXF2_HEAD); regs_buff[39] = AT_READ_REG(hw, REG_HOST_RXF2_TAIL); regs_buff[40] = AT_READ_REG(hw, REG_HOST_RXF3_HEAD); regs_buff[41] = AT_READ_REG(hw, REG_HOST_RXF3_TAIL); // mail box regs_buff[42] = AT_READ_REG(hw, REG_HOST_RXF0_WADDR); regs_buff[43] = AT_READ_REG(hw, REG_HOST_RXF1_WADDR); regs_buff[44] = AT_READ_REG(hw, REG_HOST_RXF2_WADDR); regs_buff[45] = AT_READ_REG(hw, REG_HOST_RXF3_WADDR); regs_buff[46] = AT_READ_REG(hw, REG_TPD_CONS_IDX); regs_buff[47] = AT_READ_REG(hw, REG_MB_RXF0_RADDR); regs_buff[48] = AT_READ_REG(hw, REG_MB_RXF1_RADDR); regs_buff[49] = AT_READ_REG(hw, REG_MB_RXF2_RADDR); regs_buff[50] = AT_READ_REG(hw, REG_MB_RXF3_RADDR); regs_buff[51] = AT_READ_REG(hw, REG_MB_TPD_PROD_IDX); // RSS regs_buff[52] = AT_READ_REG(hw, REG_RSS_KEY0); regs_buff[53] = AT_READ_REG(hw, REG_RSS_KEY1); regs_buff[54] = AT_READ_REG(hw, REG_RSS_KEY2); regs_buff[55] = AT_READ_REG(hw, REG_RSS_KEY3); regs_buff[56] = AT_READ_REG(hw, REG_RSS_HASH_VALUE); regs_buff[57] = AT_READ_REG(hw, REG_RSS_HASH_FLAG); regs_buff[58] = AT_READ_REG(hw, REG_IDT_TABLE); regs_buff[59] = AT_READ_REG(hw, REG_BASE_CPU_NUMBER); // TXQ regs_buff[60] = AT_READ_REG(hw, REG_TXQ_CTRL); regs_buff[61] = AT_READ_REG(hw, REG_TX_JUMBO_TASK_TH); // RXQ regs_buff[62] = AT_READ_REG(hw, REG_RXQ_CTRL); regs_buff[63] = AT_READ_REG(hw, REG_RXQ_JMBOSZ_RRDTIM); regs_buff[64] = AT_READ_REG(hw, REG_RXQ_RXF_PAUSE_THRESH); // DMA regs_buff[65] = AT_READ_REG(hw, REG_DMA_CTRL); // misc regs_buff[66] = AT_READ_REG(hw, REG_SMB_STAT_TIMER); regs_buff[67] = AT_READ_REGW(hw, REG_TRIG_RRD_THRESH); regs_buff[68] = AT_READ_REGW(hw, REG_TRIG_TPD_THRESH); regs_buff[69] = AT_READ_REGW(hw, REG_TRIG_RXTIMER); regs_buff[70] = AT_READ_REGW(hw, REG_TRIG_TXTIMER); regs_buff[71] = AT_READ_REG(hw, REG_ISR); regs_buff[72] = AT_READ_REG(hw, REG_IMR); */ atl1e_read_phy_reg(hw, MII_BMCR, &phy_data); regs_buff[73] = (u32)phy_data; atl1e_read_phy_reg(hw, MII_BMSR, &phy_data); regs_buff[74] = (u32)phy_data; }