static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info) { /* set the initial vs/emph on the source */ atombios_dig_transmitter_setup(dp_info->encoder, ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, 0, dp_info->train_set[0]); /* sets all lanes at once */ /* set the vs/emph on the sink */ radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET, dp_info->train_set, dp_info->dp_lane_count, 0); }
static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector, struct drm_encoder *encoder, u8 train_set[4]) { struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; int i; for (i = 0; i < dig_connector->dp_lane_count; i++) atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH, i, train_set[i]); radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET, dig_connector->dp_lane_count, train_set); }