static void restore_core_regs(void) { /* restore clock configuration. Writing CPUPLL last will * stall a bit and stabilize other clocks (unless this is * one of those Au1000 with a write-only PLL, where we dont * have a valid value) */ alchemy_wrsys(sleep_sys_clocks[0], AU1000_SYS_FREQCTRL0); alchemy_wrsys(sleep_sys_clocks[1], AU1000_SYS_FREQCTRL1); alchemy_wrsys(sleep_sys_clocks[2], AU1000_SYS_CLKSRC); alchemy_wrsys(sleep_sys_clocks[4], AU1000_SYS_AUXPLL); if (!au1xxx_cpu_has_pll_wo()) alchemy_wrsys(sleep_sys_clocks[3], AU1000_SYS_CPUPLL); alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC); /* Restore the static memory controller configuration. */ alchemy_wrsmem(sleep_static_memctlr[0][0], AU1000_MEM_STCFG0); alchemy_wrsmem(sleep_static_memctlr[0][1], AU1000_MEM_STTIME0); alchemy_wrsmem(sleep_static_memctlr[0][2], AU1000_MEM_STADDR0); alchemy_wrsmem(sleep_static_memctlr[1][0], AU1000_MEM_STCFG1); alchemy_wrsmem(sleep_static_memctlr[1][1], AU1000_MEM_STTIME1); alchemy_wrsmem(sleep_static_memctlr[1][2], AU1000_MEM_STADDR1); alchemy_wrsmem(sleep_static_memctlr[2][0], AU1000_MEM_STCFG2); alchemy_wrsmem(sleep_static_memctlr[2][1], AU1000_MEM_STTIME2); alchemy_wrsmem(sleep_static_memctlr[2][2], AU1000_MEM_STADDR2); alchemy_wrsmem(sleep_static_memctlr[3][0], AU1000_MEM_STCFG3); alchemy_wrsmem(sleep_static_memctlr[3][1], AU1000_MEM_STTIME3); alchemy_wrsmem(sleep_static_memctlr[3][2], AU1000_MEM_STADDR3); }
static void restore_core_regs(void) { /* restore clock configuration. Writing CPUPLL last will * stall a bit and stabilize other clocks (unless this is * one of those Au1000 with a write-only PLL, where we dont * have a valid value) */ au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); au_writel(sleep_sys_clocks[2], SYS_CLKSRC); au_writel(sleep_sys_clocks[4], SYS_AUXPLL); if (!au1xxx_cpu_has_pll_wo()) au_writel(sleep_sys_clocks[3], SYS_CPUPLL); au_sync(); au_writel(sleep_sys_pinfunc, SYS_PINFUNC); au_sync(); #ifndef CONFIG_SOC_AU1200 au_writel(sleep_usb[0], USB_HOST_CONFIG); au_writel(sleep_usb[1], USBD_ENABLE); au_sync(); #else /* enable access to OTG memory */ au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); au_sync(); /* restore OTG caps and port mux. */ au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ au_sync(); au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ au_sync(); #endif /* Restore the static memory controller configuration. */ au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); }
/* * We read the real processor speed from the PLL. This is important * because it is more accurate than computing it from the 32 KHz * counter, if it exists. If we don't have an accurate processor * speed, all of the peripherals that derive their clocks based on * this advertised speed will introduce error and sometimes not work * properly. This function is futher convoluted to still allow configurations * to do that in case they have really, really old silicon with a * write-only PLL register. -- Dan */ unsigned long au1xxx_calc_clock(void) { unsigned long cpu_speed; unsigned long flags; spin_lock_irqsave(&time_lock, flags); /* * On early Au1000, sys_cpupll was write-only. Since these * silicon versions of Au1000 are not sold by AMD, we don't bend * over backwards trying to determine the frequency. */ if (au1xxx_cpu_has_pll_wo()) #ifdef CONFIG_SOC_AU1000_FREQUENCY cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; #else cpu_speed = 396000000; #endif else
static void restore_core_regs(void) { /* restore clock configuration. Writing CPUPLL last will * stall a bit and stabilize other clocks (unless this is * one of those Au1000 with a write-only PLL, where we dont * have a valid value) */ au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); au_writel(sleep_sys_clocks[2], SYS_CLKSRC); au_writel(sleep_sys_clocks[4], SYS_AUXPLL); if (!au1xxx_cpu_has_pll_wo()) au_writel(sleep_sys_clocks[3], SYS_CPUPLL); au_sync(); au_writel(sleep_sys_pinfunc, SYS_PINFUNC); au_sync(); #ifndef CONFIG_SOC_AU1200 au_writel(sleep_usb[0], USB_HOST_CONFIG); au_writel(sleep_usb[1], USBD_ENABLE); au_sync(); #else /* enable accces to OTG memory */ au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); au_sync(); /* restore OTG caps and port mux. */ au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ au_sync(); au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ au_sync(); #endif /* Restore the static memory controller configuration. */ au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); /* * Enable the UART if it was enabled before sleep. * I guess I should define module control bits........ */ if (sleep_uart0_enable & 0x02) { au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync(); au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync(); au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync(); au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync(); au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync(); au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync(); au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync(); } restore_au1xxx_intctl(); #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) au1xxx_dbdma_resume(); #endif }