static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) { _auide_hwif *auide = &auide_hwif; dbdev_tab_t source_dev_tab, target_dev_tab; u32 dev_id, tsize, devwidth, flags; dev_id = IDE_DDMA_REQ; tsize = 8; /* 1 */ devwidth = 32; /* 16 */ #ifdef IDE_AU1XXX_BURSTMODE flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; #else flags = DEV_FLAGS_SYNC; #endif /* setup dev_tab for tx channel */ auide_init_dbdma_dev( &source_dev_tab, dev_id, tsize, devwidth, DEV_FLAGS_OUT | flags); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); auide_init_dbdma_dev( &source_dev_tab, dev_id, tsize, devwidth, DEV_FLAGS_IN | flags); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); /* We also need to add a target device for the DMA */ auide_init_dbdma_dev( &target_dev_tab, (u32)DSCR_CMD0_ALWAYS, tsize, devwidth, DEV_FLAGS_ANYUSE); auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); /* Get a channel for TX */ auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, auide->tx_dev_id, auide_ddma_tx_callback, (void*)auide); /* Get a channel for RX */ auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, auide->target_dev_id, auide_ddma_rx_callback, (void*)auide); auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, NUM_DESCRIPTORS); auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, NUM_DESCRIPTORS); /* FIXME: check return value */ (void)ide_allocate_dma_engine(hwif); au1xxx_dbdma_start( auide->tx_chan ); au1xxx_dbdma_start( auide->rx_chan ); return 0; }
static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) { _auide_hwif *auide = &auide_hwif; dbdev_tab_t source_dev_tab, target_dev_tab; u32 dev_id, tsize, devwidth, flags; dev_id = hwif->ddma_id; tsize = 8; devwidth = 32; #ifdef IDE_AU1XXX_BURSTMODE flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; #else flags = DEV_FLAGS_SYNC; #endif auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, DEV_FLAGS_OUT | flags, auide->regbase); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); auide_init_dbdma_dev(&source_dev_tab, dev_id, tsize, devwidth, DEV_FLAGS_IN | flags, auide->regbase); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); auide_init_dbdma_dev(&target_dev_tab, (u32)DSCR_CMD0_ALWAYS, tsize, devwidth, DEV_FLAGS_ANYUSE, auide->regbase); auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab); auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id, auide->tx_dev_id, auide_ddma_tx_callback, (void*)auide); auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, auide->target_dev_id, auide_ddma_rx_callback, (void*)auide); auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, NUM_DESCRIPTORS); auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, NUM_DESCRIPTORS); (void)ide_allocate_dma_engine(hwif); au1xxx_dbdma_start( auide->tx_chan ); au1xxx_dbdma_start( auide->rx_chan ); return 0; }
static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d) { _auide_hwif *auide = &auide_hwif; dbdev_tab_t source_dev_tab; int flags; #ifdef IDE_AU1XXX_BURSTMODE flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE; #else flags = DEV_FLAGS_SYNC; #endif /* setup dev_tab for tx channel */ auide_init_dbdma_dev( &source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, DEV_FLAGS_OUT | flags); auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); auide_init_dbdma_dev( &source_dev_tab, (u32)DSCR_CMD0_ALWAYS, 8, 32, DEV_FLAGS_IN | flags); auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab ); /* Get a channel for TX */ auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS, auide->tx_dev_id, NULL, (void*)auide); /* Get a channel for RX */ auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id, DSCR_CMD0_ALWAYS, NULL, (void*)auide); auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan, NUM_DESCRIPTORS); auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan, NUM_DESCRIPTORS); au1xxx_dbdma_start( auide->tx_chan ); au1xxx_dbdma_start( auide->rx_chan ); return 0; }