int mtx1_pci_idsel(unsigned int devsel, int assert) { #define MTX_IDSEL_ONLY_0_AND_3 0 #if MTX_IDSEL_ONLY_0_AND_3 if (devsel != 0 && devsel != 3) { printk(KERN_ERR "*** not 0 or 3\n"); return 0; } #endif if (assert && devsel != 0) /* Suppress signal to Cardbus */ au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */ else au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ au_sync_udelay(1); return 1; }
int mtx1_pci_idsel(unsigned int devsel, int assert) { #define MTX_IDSEL_ONLY_0_AND_3 0 #if MTX_IDSEL_ONLY_0_AND_3 if (devsel != 0 && devsel != 3) { printk(KERN_ERR "*** not 0 or 3\n"); return 0; } #endif if (assert && devsel != 0) /* Suppress signal to Cardbus */ gpio_set_value(1, 0); /* set EXT_IO3 OFF */ else gpio_set_value(1, 1); /* set EXT_IO3 ON */ au_sync_udelay(1); return 1; }
int mtx1_pci_idsel(unsigned int devsel, int assert) { #define MTX_IDSEL_ONLY_0_AND_3 0 #if MTX_IDSEL_ONLY_0_AND_3 if (devsel != 0 && devsel != 3) { printk("*** not 0 or 3\n"); return 0; } #endif if (assert && devsel != 0) { // suppress signal to cardbus au_writel( 0x00000002, SYS_OUTPUTCLR ); // set EXT_IO3 OFF } else { au_writel( 0x00000002, SYS_OUTPUTSET ); // set EXT_IO3 ON } au_sync_udelay(1); return 1; }